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january 2013 i ? 2013 microsemi corporation fusion family of mixed signal fpgas features and benefits high-performance reprogrammable flash technology ? advanced 130-nm, 7-layer metal, flash-based cmos process ? nonvolatile, retains program when powered off ? instant on single-chip solution ? 350 mhz system performance embedded flash memory ? user flash memory ? 2 mbits to 8 mbits ? configurable 8-, 16-, or 32-bit datapath ? 10 ns access in read-ahead mode ? 1 kbit of additional flashrom integrated a/d converte r (adc) and analog i/o ? up to 12-bit resolution and up to 600 ksps ? internal 2.56 v or external reference voltage ? adc: up to 30 scalable analog input channels ? high-voltage input tolerance: ?10.5 v to +12 v ? current monitor and temperature monitor blocks ? up to 10 mosfet gate driver outputs ? p- and n-channel power mosfet support ? programmable 1, 3, 10, 30 a, and 20 ma drive strengths ? adc accuracy is better than 1% on-chip clocking support ? internal 100 mhz rc oscillator (accurate to 1%) ? crystal oscillator support (32 khz to 20 mhz) ? programmable real-time counter (rtc) ? 6 clock conditioning circuits (cccs) with 1 or 2 integrated plls ? phase shift, multiply/divide, and delay capabilities ? frequency: input 1.5?350 mhz, output 0.75?350 mhz low power consumption ? single 3.3 v power supply with on-chip 1.5 v regulator ? sleep and standby low-power modes in-system programming (isp) and security ? isp with 128-bit aes via jtag ? flashlock ? designed to protect fpga contents advanced digital i/o ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages ? up to 5 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v /1.8 v / 1.5 v, 3.3 v pci / 3.3 v pci-x, and lvcmos 2.5 v / 5.0 v input ? differential i/o standards: lvpecl, lvds, b-lvds, m-lvds ? built-in i/o registers ? 700 mbps ddr operation ? hot-swappable i/os ? programmable output slew rate, drive strength, and weak pull-up/down resistor ? pin-compatible packages across the fusion ? family srams and fifos ? variable-aspect-ratio 4,608-bit sram blocks (1, 2, 4, 9, and 18 organizations available) ? true dual-port sram (except 18) ? programmable embedded fifo control logic soft arm cortex-m1 fusion devices (m1) ?arm ? cortex-?m1?enabled pigeon point atca ip support (p1) ? targeted to pigeon point ? board management reference (bmr) starter kits ? designed in partnership with pigeon point systems ? arm cortex-m1 enabled microblade advanced mezz anine card support (u1) ? targeted to advanced mezzanine card (advancedmc? designs) ? designed in partnership with microblade ? 8051-based module management controller (mmc) table 1 ? fusion family fusion devices afs090 af s250 afs600 afs1500 arm cortex-m1 * devices m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 p1afs1500 microblade devices u1afs250 u1afs600 u1afs1500 general information system gates 90,000 250,000 600,000 1,500,000 tiles (d-flip-flops) 2,304 6,144 13,824 38,400 secure (aes) isp yes yes yes yes plls 1122 globals 18 18 18 18 memory flash memory blocks (2 mbits) 1 1 2 4 total flash memory bits 2m 2m 4m 8m flashrom bits 1,024 1,024 1,024 1,024 ram blocks (4,608 bits) 6 8 24 60 ram kbits 27 36 108 270 analog and i/os analog quads 5 6 10 10 analog input channels 15 18 30 30 gate driver outputs 5 6 10 10 i/o banks (+ jtag) 4 4 5 5 maximum digital i/os 75 114 172 252 analog i/os 20 24 40 40 note: *refer to the cortex-m1 product brief for more information. revision 4
fusion family of mixed signal fpgas ii revision 4 fusion device architecture overview package i/os: single-/double-ended (analog) figure 1 ? fusion device architecture overview (afs600) fusion devices afs090 afs250 afs600 afs1500 arm cortex-m1 devices m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 1 p1afs1500 1 microblade devices u1afs250 2 u1afs600 2 u1afs1500 2 qn108 37/9 (16) qn180 60/16 (20) 65/15 (24) pq208 3 93/26 (24) 95/46 (40) fg256 75/22 (20) 114/37 (24) 119/58 (40) 119/58 (40) fg484 172/86 (40) 223/109 (40) fg676 252/126 (40) notes: 1. pigeon point devices are only offered in fg484 and fg256. 2. microblade devices are only offered in fg256. 3. fusion devices in the same package are pin compatible wit h the exception of the pq208 package (afs250 and afs600). versatile ccc ccc i/os osc ccc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad
fusion family of mixed signal fpgas revision 4 iii product ordering codes fusion device status notes: 1. for fusion devices, quad flat no lead packages are only offered as rohs compliant, qng packages. 2. microblade and pigeon point devices only support fg packages. fusion status cortex-m1 status pig eon point status microblade status afs090 production afs250 production m1afs250 production u1afs250 production afs600 production m1afs600 production p1afs600 production u1afs600 production afs1500 production m1afs1500 production p1afs1500 production u1afs1500 production m1afs600 fg _ part number fusion devices speed grade 1 blank = standard 1 = 15% faster than standard 2 = 25% faster than standard package type qn = quad flat no lead (0.5 mm pitch) 256 i g package lead count y security feature application (junction temperature range) blank = commercial (0 to +85c) i = industrial (?40 to +100c) pp = pre-production es = engineering silicon (room temperature only) 90,000 system gates afs090 = 250,000 system gates afs250 = arm-enabled fusion devices 600,000 system gates afs600 = 1,500,000 system gates afs1500 = microblade devices 250,000 system gates u1afs250 = 600,000 system gates u1afs600 = 1,500,000 system gates u1afs1500 = pigeon point devices 600,000 system gates p1afs600 = 1,500,000 system gates p1afs1500 = 250,000 system gates m1afs250 = 600,000 system gates m1afs600 = 1,500,000 system gates m1afs1500 = pq = plastic quad flat pack (0.5 mm pitch) fg = fine pitch ball grid array (1.0 mm pitch) lead-free packaging options blank = standard packaging g = rohs-compliant (green) packaging 1 2 y = device includes license to implement ip based on the cryptography research, inc. (cri) patent portfolio blank = device does not include license to implement ip based on the cryptography research, inc. (cri) patent portfolio
fusion family of mixed signal fpgas iv revision 4 temperature grade offerings speed grade and temperature grade matrix contact your local microsemi soc products gr oup representative for device availability: http://www.microsemi.com/soc/contact/offices/index.html . cortex-m1, pigeon point, and micr oblade fusion device information this datasheet provides information for a ll fusion (afs), cortex-m1 (m1), pigeon poin t (p1), and microblade (u1) devices. the remainder of the document will only list the fusion (afs) devices. please apply relevant information to m1, p1, and u1 devices when appropriate. please note the following: ? cortex-m1 devices are offered in the same speed grades and packages as basic fusion devices. ? pigeon point devices are only offered in ?2 speed grade and fg484 and fg256 packages. ? microblade devices are only offered in standard speed grade and the fg256 package. fusion devices afs090 afs250 afs600 afs1500 arm cortex-m1 devices m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 3 p1afs1500 3 microblade devices u1afs250 4 u1afs600 4 u1afs1500 4 qn108 c, i ? ? ? qn180 c, i c, i ? ? pq208 ? c, i c, i ? fg256 c, ic, ic, ic, i fg484 ? ? c, i c, i fg676 ???c, i notes: 1. c = commercial temperature range: 0c to 85c junction 2. i = industrial temperature range: ?40c to 100c junction 3. pigeon point devices are only offered in fg484 and fg256. 4. microblade devices are only offered in fg256. std. 1 ?1 ?2 2 c 3 333 i 4 333 notes: 1. microblade devices are only offered in standard speed grade. 2. pigeon point devices are only offered in ?2 speed grade. 3. c = commercial temperature range: 0c to 85c junction 4. i = industrial temperature range: ?40c to 100c junction
fusion family of mixed signal fpgas revision 4 v table of contents fusion device family overview introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 unprecedented integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 device architecture fusion stack architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 clocking resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 real-time counter system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 embedded memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 analog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 analog configuration mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129 user i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-135 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-226 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-231 dc and power characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 package pin assignments qn108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 qn180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 pq208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 fg256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 fg484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 fg676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

revision 4 1-1 1 ? fusion device family overview introduction the fusion mixed signal fpga satisfies the demand from system architects for a device that simplifies design and unleashes their creativity. as the world?s first mixed signal programmable logic family, fusion integrates mixed signal analog, flash memory, and fpga fabric in a monolithic device. fusion devices enable designers to quickly move from concept to completed design and then deliver feature-rich systems to market. this new technology takes advant age of the unique properties of microsemi flash- based fpgas, including a high-isolation, triple-we ll process and the ability to support high-voltage transistors to meet the demanding requ irements of mixed signal system design. fusion mixed signal fpgas bring the benefits of programmable logic to many application areas, including power management, smart battery char ging, clock generation and management, and motor control. until now, these applications have only been implemented with costly and space-consuming discrete analog components or mixed signal asic solutions. fusion mixed signal fpgas present new capabilities for system devel opment by allowing de signers to integrat e a wide range of fu nctionality into a single device, while at the same time offering the fl exibility of upgrades late in the manufacturing process or after the device is in the field. fusion devices provide an excellent alternative to costly and time- consuming mixed signal asic designs. in addition , when used in conjunction with the arm cortex-m1 processor, fusion technology represents the definitive mixed signal fpga platform. flash-based fusion devices are instant on. as so on as system power is applied and within normal operating specifications, fusion devices are working. fusion devices have a 128-bit flash-based lock and industry-leading aes decryption, used to secure pr ogrammed intellectual property (ip) and configuration data. fusion devices are the most comprehensive single-chip analog and digital programmable logic solution available today. to support this new ground-breaking technology, microsemi has developed a series of major tool innovations to help maximize designer productivity. implemented as extensions to the popular microsemi libero ? system-on-chip (soc) software, these new tools allow designers to easily instantiate and configure peripherals within a design, establish links between peripherals, create or import building blocks or reference designs, and perform hardware verification. this tool suite will also add comprehensive hardware/software debug capability as well as a suite of utilities to simplify development of embedded soft-processor-based solutions. general description the fusion family, based on the highly successful proasic ? 3 and proasic3e flash fpga architecture, has been designed as a high-performance, programm able, mixed signal platform. by combining an advanced flash fpga core with flash memory blocks and analog periph erals, fusion devices dramatically simplify system design and, as a re sult, dramatically reduce overall system cost and board space. the state-of-the-art flash memory technology of fers high-density integrated flash memory blocks, enabling savings in cost, power, and board area relative to external flash solutions, while providing increased flexibility and performanc e. the flash memory blocks and in tegrated analog pe ripherals enable true mixed-mode programmable logic designs. two ex amples are using an on-chip soft processor to implement a fully functional flash mcu and usin g high-speed fpga logic to offer system and power supervisory capabilities. instant on, and capable of operating from a single 3.3 v supply, the fusion family is ideally suit ed for system management and control applications. the devices in the fusion family are categorized by fpga core density. each family member contains many peripherals, including flash memory blocks, an analog-to-digital-converter (adc), high-drive outputs, both rc and crystal oscillators, and a real-tim e counter (rtc). this provides the user with a high level of flexibility and integration to support a wide variety of mixed signal applications. the flash memory block capacity ranges from 2 mbits to 8 mbits. the integrated 12 -bit adc supports up to 30 independently configurable input channels.
fusion device family overview 1-2 revision 4 the on-chip crystal and rc oscillators work in conj unction with the integrated phase-locked loops (plls) to provide clocking support to the fpga array and on -chip resources. in addition to supporting typical rtc uses such as watchdog timer, the fusion rtc can control the on-chip voltage regulator to power down the device (fpga fabric, flash memory block, and adc), enabling a low power standby mode. the fusion family offers revolutionary features, never before available in an fpga. the nonvolatile flash technology gives the fusion solution the advantage of being a highly secure, low power, single-chip solution that is instant on. fusion is reprogrammable and offers time-to-market benefits at an asic-level unit cost. these features enable designers to cr eate high-density systems us ing existing asic or fpga design flows and tools. flash advantages reduced cost of ownership advantages to the designer extend beyond low unit cost, high performance, an d ease of use. flash- based fusion devices are instant on and do not need to be loaded from an external boot prom. on- board security mechanisms prevent access to t he programming information and enable remote updates of the fpga logic that are protected with high leve l security. designers can perform remote in-system reprogramming to support future design iterations and field upgrades, with confidence that valuable ip is highly unlikely to be compromised or copied. isp can be performed using the industry-standard aes algorithm with mac data authenticati on on the device. the fusion fami ly device architecture mitigates the need for asic migration at higher user volumes. this makes the fusion fam ily a cost-effective asic replacement solution for applications in the consum er, networking and communications, computing, and avionics markets. security as the nonvolatile, flash-based fusion family requi res no boot prom, there is no vulnerable external bitstream. fusion devices incorporate flashlock, which provides a unique combination of reprogrammability and design security without exte rnal overhead, advantages that only an fpga with nonvolatile flash programming can offer. fusion devices utilize a 128-bit flash-based key lock and a separate aes key to provide the highest level of protection in the fpga industry for programme d ip and configuration data. the flashrom data in fusion devices can also be encrypted prior to loading. additionally, the flash memory blocks can be programmed during runtime using the industry-lead ing aes-128 block cipher encryption standard (fips publication 192). the aes standard was adopted by the national inst itute of standards and technology (nist) in 2000 and replaces the des standard, which was adopted in 1977. fusion devices have a built- in aes decryption engine and a flash-based aes key th at make fusion devices the most comprehensive programmable logic device securi ty solution available today. fusi on devices with aes-based security provide a high level of protection for remote field updat es over public networks, such as the internet, and are designed to ensure that valuable ip remains out of t he hands of system overbu ilders, system cloners, and ip thieves. as an additional security measure, the fpga configuration data of a programmed fusion device cannot be read back, although secure design verification is possible. during design, the user controls and defines both internal and external access to the flash memory blocks. security, built into the fpga fabric, is an inheren t component of the fusion family. the flash cells are located beneath seven metal layers, and many devi ce design and layout techniques have been used to make invasive attacks extremely difficult. fusion with flashlock and aes security is unique in being highly resistant to both invasive and noninvasive atta cks. your valuable ip is protected with industry- standard security, making remote isp possible. a fusion device provides the best available security for programmable logic designs. single chip flash-based fpgas store their configuration informati on in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga st ructure, and no external configuration data needs to be loaded at system power-up (unlike sram-based fpgas). therefore, flash-based fusion fpgas do not require system configuration components such as eeproms or microcontrollers to load device configuration data. this reduces bill-of-materials co sts and pcb area, and incr eases security and system reliability.
fusion family of mixed signal fpgas revision 4 1-3 instant on flash-based fusion devices are level 0 instant on. instant on fusion devices greatly simplify total system design and reduce total system cost by elim inating the need for cplds. the fusion instant on clocking (plls) replaces off-chip clocking resources. the fusion mix of instant on clocking and analog resources makes these devices an ex cellent choice for both system supervisor and system management functions. instant on from a single 3.3 v source enabl es fusion devices to initiate, control, and monitor multiple voltage supplies while also providing syst em clocks. in addition, glitches and brownouts in system power will not corrupt the fu sion device flash conf iguration. unlike sram-based fpgas, the device will not have to be reloaded when system power is restored. this enables reduction or complete removal of expensive voltage monitor and brownout detection devices from the pcb design. flash- based fusion devices simplify total system design and reduce cost and design risk, while increasing system reliability. firm errors firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or i/o behavio r in an unpredictable way. another source of radiation-induced firm errors is alpha particles. for an alpha to cause a soft or firm error, its source must be in very close proxim ity to the affected circuit. the alpha source must be in the package molding compound or in the die itself. while low-alpha molding compounds are being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors. firm errors are impossible to prevent in sram fp gas. the consequence of this type of error can be a complete system failure. firm errors do not occur in fusion flash-bas ed fpgas. once it is programmed, the flash cell configuration element of fusion fpga s cannot be altered by high-energy neutrons and is therefore immune to errors from them. recoverable (or soft) errors occur in the user data srams of all fpga devi ces. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. low power flash-based fusion devices exhibit power characteri stics similar to those of an asic, making them an ideal choice for power-sensitive applications. with fusion devices, there is no power-on current surge and no high current transition, both of which occur on many fpgas. fusion devices also have low dynamic power consumption and support both low power standby mode and very low power sleep mode, offering further power savings. advanced flash technology the fusion family offers many benefits, includi ng nonvolatility and reprogrammability through an advanced flash-based, 130-nm lvcmos process with seven layers of metal. standard cmos design techniques are used to implement logic and contro l functions. the combination of fine granularity, enhanced flexible routing resources, and abundant flas h switches allows very high logic utilization (much higher than competing sram technologies) with out compromising device routability or performance. logic functions within the device are interconn ected through a four-level routing hierarchy. advanced architecture the proprietary fusion architecture provides granula rity comparable to standard-cell asics. the fusion device consists of several distinct and programma ble architectural features , including the following ( figure 1-1 on page 1-5 ): ? embedded memories ? flash memory blocks ?flashrom ? sram and fifo ? clocking resources ? pll and ccc
fusion device family overview 1-4 revision 4 ? rc oscillator ? crystal oscillator ? no-glitch mux (ngmux) ? digital i/os with advanced i/o standards ? fpga versatiles ? analog components ?adc ? analog i/os supporting voltage, current, and temperature monitoring ? 1.5 v on-board voltage regulator ? real-time counter the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic lookup table (lut) equivalent or a d-flip-flop or latch (with or without enable) by programming the appropriate flash switch interconnections. this versat ility allows efficient use of the fpga fabric. the versatile capability is unique to the microsemi fam ilies of flash-based fpgas. versatiles and larger functions are connected with any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, re configurable interconnect programming. maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circuitry allows for rapid (3.3 v) single-voltage programming of fusion devices via an ieee 1532 jtag interface. unprecedented integration integrated analog bl ocks and analog i/os fusion devices offer robust and flexible analog mixed signal capability in addition to the high- performance flash fpga fabric and flash memory blo ck. the many built-in analog peripherals include a configurable 32:1 input analog mux, up to 10 independent mosfet gate driver outputs, and a configurable adc. the adc supports 8-, 10-, and 12 -bit modes of operation with a cumulative sample rate up to 600 k samples per second (ksps), diff erential nonlinearity (dnl) < 1.0 lsb, and total unadjusted error (tue) of 0.72 lsb in 10-bit mode . the tue is used for characterization of the conversion error and includes errors from all source s, such as offset and linearity. internal bandgap circuitry offers 1% voltage reference accuracy with t he flexibility of utilizing an external reference voltage. the adc channel sampling sequence and sampling rate are programmable and implemented in the fpga logic using designer and libero soc software tool support. two channels of the 32-channel adcm ux are dedicated. channel 0 is connected internally to vcc and can be used to monitor core power supply. channel 31 is connected to an internal temperature diode which can be used to monitor device temperature. the 30 remaining channels can be connected to external analog signals. the exact number of i/os available for external connection signals is device- dependent (refer to the "fusion family" table on page i for details). with fusion, microsemi also introduc es the analog quad i/o structure ( figure 1-1 on page 1-5 ). each quad consists of three analog inputs and one gate dr iver. each quad can be configured in various built-in circuit combinations, such as three prescaler circuits, three digital input circuits, a current monitor circuit, or a temperature monitor circuit. each prescale r has multiple scaling factors programmed by fpga signals to support a large range of analog inputs with positive or negative polarity. when the current monitor circuit is selected, two adjacent analog in puts measure the voltage drop across a small external sense resistor. for more information, refer to the "analog system characteristics" section on page 2-120 . built-in operational amplifiers amplif y small voltage signals for accurate current measurement. one analog input in each quad can be connected to an external temperature monitor diode. in addition to the external temperature moni tor diode(s), a fusion device can monitor an internal temperature diode using dedicated channel 31 of the adcmux. figure 1-1 on page 1-5 illustrates a typical use of the anal og quad i/o structure. the analog quad shown is configured to monitor and control an exte rnal power supply. the av pad measures the source of the power supply. the ac pad measures the voltage drop across an external sense resistor to
fusion family of mixed signal fpgas revision 4 1-5 calculate current. the ag mosfet gate driver pad tu rns the external mosfet on and off. the at pad measures the load-side voltage level. embedded memories flash memory blocks the flash memory available in each fu sion device is composed of one to four flash blocks, each 2 mbits in density. each block operates independently with a dedicated flash controller and interface. fusion flash memory blocks combine fast access times (60 ns random access and 10 ns access in read-ahead mode) with a configurable 8-, 16-, or 32-bit datapath, enabling high- speed flash operation without wait states. the memory block is organized in pages and sectors. each page has 128 bytes, with 33 pages comprising one sector and 64 sectors per block. the fl ash block can support multiple partitions. the only constraint on size is that partition boundaries must coincide with page boundaries. the flexibility and granularity enable many use models and allo w added granularity in programming updates. fusion devices support two methods of external access to the flash memory blocks. the first method is a serial interface that f eatures a built-in jtag-compliant port, which allows in-system programmability during user or monitor/test modes. this serial in terface supports programming of an aes-encrypted stream. data protected with security measures c an be passed through the jtag interface, decrypted, and then programmed in the flash block. the second method is a soft parallel interface. fpga logic or an on-chip soft microprocessor can a ccess flash memory through the parallel interface. since the flash parallel interface is implemented in the fpga fabric, it can potentially be customized to meet special user requirements. for more information, refer to the corecfi handbook. the flash memory parallel interface provides configurable by te-wide (8), word-wide (16), or dual-word-wide figure 1-1 ? analog quad analog quad av ac at voltage monitor block current monitor block ag power line side load side pre- scaler digital input power mosfet gate driver current monitor/instr amplifier temperature monitor digital input digital input pre- scaler pre- scaler pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip r pullup from fpga (gdonx)
fusion device family overview 1-6 revision 4 (32) data-port options. through the programmable fl ash parallel interface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations. the flash memory has built-in security. the user can co nfigure either the entire flash block or the small blocks to protect against unintentional or intrusive attempts to change or destroy the storage contents. each on-chip flash memory block has a dedicated controller, enabling each block to operate independently. the flash block logic consists of the following sub-blocks: ? flash block ? contains all stored data. the flash block contains 64 sectors and each sector contains 33 pages of data. ? page buffer ? contains the contents of the current page being modified. a page contains 8 blocks of data. ? block buffer ? contains the contents of the last block accessed. a block contains 128 data bits. ? ecc logic ? the flash memory stores error correction information with each block to perform single-bit error correction and double-bit error detection on all data blocks. user nonvolatile flashrom in addition to the flash bl ocks, fusion devices have 1 kbit of user -accessible, nonvolatile flashrom on- chip. the flashrom is organized as 8128-bit page s. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business models (for example, set-top boxes) ? secure key storage for communicatio ns algorithms protected by security ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard ieee 1532 jtag programming interface. pages can be individually programmed (erased and written). on-chip aes decryptio n can be used selectively over public networks to load data such as security ke ys stored in the flashrom for a user design. the flashrom can be programmed (erased and writt en) via the jtag programming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. the flashpoint tool in the fusion development software solutions, libero soc and designer, has extensive support for flash memory blocks and fl ashrom. one such featur e is auto-generation of sequential programming files for applications requir ing a unique serial number in each part. another feature allows the inclusion of st atic data for system version contro l. data for the flashrom can be generated quickly and easily using the libero soc and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing flashrom contents. sram and fifo fusion devices have embedded sram blocks along the north and so uth sides of the device. each variable-aspect-ratio sram block is 4,608 bits in size. available memory configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. the individual bl ocks have independent read and write ports that can be configured with different bit widths on each port. fo r example, data can be written through a 4-bit port and read as a single bitstream. the sram blocks can be initialized from the flash memory blocks or via the device jtag port (rom emulation mode), using the ujtag macro. in addition, every sram block has an embedded fi fo control unit. the contro l unit allows the sram block to be configured as a synchronous fifo with out using additional core versatiles. the fifo width and depth are programmable. the fifo also feat ures programmable almost empty (aempty) and almost full (afull) flags in addition to the no rmal empty and full flags. the embedded fifo control unit contains the counters necessary for the gen eration of the read and write address pointers. the sram/fifo blocks can be cascaded to create larger configurations.
fusion family of mixed signal fpgas revision 4 1-7 clock resources plls and clock conditi oning circuits (cccs) fusion devices provide designers with very flexible cl ock conditioning capabilities. each member of the fusion family contains six cccs. in the two larger family members, two of these cccs also include a pll; the smaller devices support one pll. the inputs of the ccc blocks are acce ssible from the fpga core or from one of several inputs with dedicated ccc block connections. the ccc block has the following key features: ? wide input frequency range (f in_ccc ) = 1.5mhz to 350mhz ? output frequency range (f out_ccc ) = 0.75 mhz to 350 mhz ? clock phase adjustment via programmable a nd fixed delays from ?6.275 ns to +8.75 ns ? clock skew minimization (pll) ? clock frequency synthesis (pll) ? on-chip analog clocking resources usable as inputs: ? 100 mhz on-chip rc oscillator ? crystal oscillator additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270 ? output duty cycle = 50% 1.5% ? low output jitter. samples of peak-to-peak period jitter when a single global network is used: ? 70 ps at 350 mhz ? 90 ps at 100 mhz ? 180 ps at 24 mhz ? worst case < 2.5% clock period ? maximum acquisition time = 150 s ? low power consumption of 5 mw global clocking fusion devices have extensive support for multiple clocking domains. in addition to the ccc and pll support described above, there are on-chip oscillators as well as a comprehensive global clock distribution network. the integrated rc oscillator generates a 100 mhz clock. it is used internally to provide a known clock source to the flash memory read and write control. it can also be used as a source for the plls. the crystal oscillator supports the following operating modes: ? crystal (32.768 khz to 20 mhz) ? ceramic (500 khz to 8 mhz) ? rc (32.768 khz to 4 mhz) each versatile input and output port has access to nine versanets: six main and three quadrant global networks. the versanets can be driven by the ccc or directly accessed from the core via muxes. the versanets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. digital i/os with ad vanced i/o standards the fusion family of fpgas features a flexible digita l i/o structure, supporting a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). fusion fpgas support many different digital i/o standards, both single-ended and differential. the i/os are organized into banks, with four or five banks per device. the configuration of these banks determines the i/o standards supported. the banks al ong the east and west sides of the device support the full range of i/o standards (single-ended and di fferential). the south bank supports the analog quads (analog i/o). in the family's two smaller devices, th e north bank supports multiple single-ended digital i/o
fusion device family overview 1-8 revision 4 standards. in the family?s larger devices, the north bank is divided into two banks of digital pro i/os, supporting a wide variety of single-ended, differential, and voltage-referenced i/o standards. each i/o module contains several input, output, and enable registers. these registers allow the implementation of the following applications: ? single-data-rate (sdr) applications ? double-data-rate (ddr) applications?ddr lvds i/o for chip-to-chip communications ? fusion banks support lvpecl, lvds, blvds, and m-lvds with 20 multi-drop points. versatiles the fusion core consists of versatiles, which are also used in the successful proasic3 family. the fusion versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set and optional enable refer to figure 1-2 for the versatile conf iguration arrangement. specifying i/o states during programming you can modify the i/o states during programming in fl ashpro. in flashpro, this feature is supported for pdb files generated from designer v8.5 or greater. see the flashpro user?s guide for more information. note: pdb files generated from designer v8.1 to designer v8.4 (including all service packs) have limited display of pin numbers only. the i/os are controlled by the jtag boundary scan re gister during programming, except for the analog pins (ac, at and av). the boundary scan register of the ag pin can be used to enable/disable the gate driver in software v9.0. 1. load a pdb from the flashpro gui. you must have a pdb loaded to modify the i/o states during programming. 2. from the flashpro gui, click pdb configuration . a flashpoint ? programming file generator window appears. 3. click the specify i/o states during programming button to display the specify i/o states during programming dialog box. 4. sort the pins as desired by clicking any of the column headers to sort the entries by that header. select the i/os you wish to modify ( figure 1-3 on page 1-9 ). 5. set the i/o output state. you can set basic i/o se ttings if you want to use the default i/o settings for your pins, or use custom i/o settings to cust omize the settings for each pin. basic i/o state settings: 1 ? i/o is set to drive out logic high 0 ? i/o is set to drive out logic low last known state ? i/o is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming z -tri-state: i/o is tristated figure 1-2 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ffe data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
fusion family of mixed signal fpgas revision 4 1-9 6. click ok to return to the flashpoint ? programming file generator window. i/o states during programming are saved to the ad b and resulting programming files after completing programming file generation. figure 1-3 ? i/o states during programming window
fusion device family overview 1-10 revision 4 related documents datasheet core8051 www.microsemi.com/soc/ipdocs/core8051_ds.pdf application notes fusion flashrom http://www.microsemi.com/soc /documents/fusion_from_an.pdf fusion sram/fifo blocks http://www.microsemi.com/soc/doc uments/fusion_ram_fifo_an.pdf using ddr in fusion devices http://www.microsemi.com/soc /documents/fusion_ddr_an.pdf fusion security http://www.microsemi.com/soc/ documents/fusion_security_an.pdf using fusion ram as multipliers http://www.microsemi.com/soc/doc uments/fusion_multipliers_an.pdf handbook cortex-m1 handbook www.microsemi.com/soc/documents/cortexm1_hb.pdf user?s guides designer user's guide http://www.microsemi.com/soc /documents/designer_ug.pdf fusion fpga fabric user?s guide http://www.microsemi.com/soc/documents/fusion_ug.pdf igloo, proasic3, smartfusion and fusion macro library guide http://www.microsemi.com/soc /documents/pa3_libguide_ug.pdf smartgen, flashrom, flash memory system builder, and analog system builder user's guide http://www.microsemi.com/s oc/documents/genguide_ug.pdf white papers fusion technology http://www.microsemi.com/soc/documents/fusion_tech_wp.pdf
revision 4 2-1 2 ? device architecture fusion stack architecture to manage the unprecedented level of integration in fusion devices, microsemi developed the fusion technology stack ( figure 2-1 ). this layered model offers a flexib le design environment, enabling design at very high and very low levels of abstraction. fusion peripherals include hard analog ip and hard and soft digital ip. peripherals communicate across the fpga fabric via a layer of soft gates?the fusion backbone. much more than a common bus interface, this fusion backbone integrates a micro-sequencer within the fpga fabric and configur es the individual peripherals and supports low-level processing of peripheral data. fusion applets are application building blocks that can control and respond to peripherals and other system signals. applets can be r apidly combined to create large applications. the technology is scalable across devices, families, desi gn types, and user expertise, and supports a well- defined interface for external ip and tool integration. at the lowest leve l, level 0, are fusion peripherals. these ar e configurable functio nal blocks that can be hardwired structures such as a pll or analog input c hannel, or soft (fpga gate) blocks such as a uart or two-wire serial interface. the fusion peripherals are configurable and support a standard interface to facilitate communication and implementation. connecting and controlling access to the peripherals is the fusion backbone, level 1. the backbone is a soft-gate structure, scalable to any number of peripherals. the backbone is a bus and much more; it manages peripheral configuration to ensure pr oper operation. leveraging the common peripheral interface and a low-level state machine, the back bone efficiently offloads peripheral management from the system design. the backbone can set and clear flags based upon peripheral behavior and can define performance criteria. the flexibility of the stack e nables a designer to configure the silicon, directly bypassing the backbone if that level of control is desired. one step up from the backbone is the fusion applet, lev el 2. the applet is an application building block that implements a specific function in fpga gates. it can react to stimuli and board-level events coming through the backbone or from other sources, and responds to these stimuli by accessing and manipulating peripherals via the backbone or initiating some other action. an applet controls or responds to the peripheral(s). applets can be easily import ed or exported from the des ign environment. the applet structure is open and well -defined, enabling users to import applets from microsemi, system developers, third parties, and user groups. note: levels 1, 2, and 3 are implemented in fpga logic gates. figure 2-1 ? fusion architecture stack flash memory analog smart peripheral 1 analog smart peripheral 2 analog smart peripheral n smart peripherals in fpga fabric (e.g., logic, pll, fifo) fusion smart backbone fusion applets user applications level 1 level 0 level 2 level 3 optional arm or 8051 processor
device architecture 2-2 revision 4 the system application, level 3, is the larger user application that utilizes one or more applets. designing at the highest level of abstraction supported by the fusion technology stack, the application can be easily created in fpga gates by importing and configuring multiple applets. in fact, in some cases an en tire fpga system design can be created without any hdl coding. an optional mcu enables a combination of software and hdl-based design methodologies. the mcu can be on-chip or off-chip as system requirements dictate. s ystem portioning is very flexible, allowing the mcu to reside above the applets or to absorb applets, or applets and backbone, if desired. the fusion technology stack enables a very flexible design environment. users can engage in design across a continuum of abstraction from very low to very high. core architecture versatile based upon successful proasic3/e logic architecture, fusion devices provide granularity comparable to gate arrays. the fusion device core consists of a sea-of-versatiles architecture. as illustrated in figure 2-2 , there are four inputs in a logic versatile cell, and each versatile can be configured using the appropriat e flash switch connections: ? any 3-input logic function ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set (on a 4th input) versatiles can flexibly map the logic and sequential ga tes of a design. the inputs of the versatile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. versatiles and larger functions are connected with any of the four levels of routing hierarchy. when the versatile is used as an enable d-flip-flop, the set/clr signal is supported by a fourth input, which can only be routed to the core cell over the versanet (global) network. the output of the versatile is f2 when the connectio n is to the ultra-fast local lines, or yl when the connection is to the efficient long-line or very-long-line resources ( figure 2-2 ). note: *this input can only be connected to the global clock distribution network. figure 2-2 ? fusion core versatile switch (flash connection) ground via (hard connection) legend: y pin 1 0 1 0 1 0 1 0 1 data x3 clk x2 clr/ enable x1 clr xc* f2 yl
fusion family of mixed signal fpgas revision 4 2-3 versatile characteristics sample versatile specifications?combinatorial module the fusion library offers all combinations of lut-3 combinatorial functions. in this section, timing characteristics are presented fo r a sample of the library ( figure 2-3 ). for more details, refer to the igloo, proasic3, smartfusion and fusion macro library guide . figure 2-3 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
device architecture 2-4 revision 4 figure 2-4 ? combinatorial timing model and waveforms t pd t pd t pd vcca vcca t pd t pd vcca t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell nand2 or any combinatorial logic a b y (rr) a, b, c out 50% gnd (ff) 50% 50% 50% gnd (rf) 50% (fr) 50% out gnd
fusion family of mixed signal fpgas revision 4 2-5 timing characteristics sample versatile specifications?sequential module the fusion library offers a wide variety of sequential cells, including flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the library ( figure 2-5 ). for more details, refer to the igloo, proasic3, smartfusion and fusion macro library guide . table 2-1 ? combinatorial cell propagation delays commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v combinatorial cell equation parameter ?2 ?1 std. units inv y = !a t pd 0.40 0.46 0.54 ns and2 y = a b t pd 0.47 0.54 0.63 ns nand2 y = !(a b) t pd 0.47 0.54 0.63 ns or2 y = a + b t pd 0.49 0.55 0.65 ns nor2 y = !(a + b) t pd 0.49 0.55 0.65 ns xor2 y = a ?? bt pd 0.74 0.84 0.99 ns maj3 y = maj(a, b, c) t pd 0.70 0.79 0.93 ns xor3 y = a ? b ?? ct pd 0.87 1.00 1.17 ns mux2 y = a !s + b s t pd 0.51 0.58 0.68 ns and3 y = a b c t pd 0.56 0.64 0.75 ns note: for the derating values at specific junction te mperature and voltage supp ly levels, refer to ta ble 3-7 o n page 3-9 .
device architecture 2-6 revision 4 figure 2-5 ? sample of sequential cells figure 2-6 ? sequential timing model and waveforms dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
fusion family of mixed signal fpgas revision 4 2-7 sequential timing characteristics table 2-2 ? register delays commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t clkq clock-to-q of the core register 0.55 0.63 0.74 ns t sud data setup time for the co re register 0.43 0.49 0.57 ns t hd data hold time for the core register 0.00 0.00 0.00 ns t sue enable setup time for the co re register 0.45 0.52 0.61 ns t he enable hold time for the core register 0.00 0.00 0.00 ns t clr2q asynchronous clear-to-q of th e core register 0.40 0.45 0.53 ns t pre2q asynchronous preset-to-q of th e core register 0.40 0.45 0.53 ns t remclr asynchronous clear removal time fo r the core register 0.00 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.22 0.25 0.30 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.22 0.25 0.30 ns t wclr asynchronous clear minimum pulse widt h for the core regi ster 0.22 0.25 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.22 0.25 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.32 0.37 0.43 ns t ckmpwl clock minimum pulse width low for the core register 0.36 0.41 0.48 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-8 revision 4 array coordinates during many place-and-route operati ons in the microsemi designer soft ware tool, it is possible to set constraints that require array coordinates. table 2-3 is provided as a reference. the array coordinates are measured from the lower left (0, 0). they ca n be used in region constraints for specific logic groups/blocks, desi gnated by a wildca rd, and can contain core ce lls, memories, and i/os. table 2-3 provides array coordinates of core cells and memory blocks. i/o and cell coordinates are us ed for placement cons traints. two coordi nate systems are needed because there is not a one-to-one correspondence between i/o cells and edge core cells. in addition, the i/o coordinate system changes depending on the di e/package combination. it is not listed in ta b l e 2 - 3 . the designer chipplanner tool provides array coordi nates of all i/o locations. i/o and cell coordinates are used for placement constraints. however, i/ o placement is easier by package pin assignment. figure 2-7 illustrates the array coordinates of an afs600 device. for more information on how to use array coordinates for region/placement constraints, see the designer user's guide or online help (available in the software) for fusion software tools. table 2-3 ? array coordinates device versatiles memory rows all min. max. bottom top min. max. x y x y (x, y) (x, y) (x, y) (x, y) afs090 3 2 98 25 none (3, 26) (0, 0) (101, 29) afs250 3 2 130 49 none (3, 50) (0, 0) (133, 53) afs600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) afs1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 129) note: the vertical i/o tile coordinates are not shown. west side coor dinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates are {(195, 2) to ( 197, 2)} to {(195, 77) to (197, 77)}. figure 2-7 ? array coordinates for afs600 (0, 79) (197, 1) top row (5, 1) to (168, 1) bottom row (7, 0) to (165, 0) top row (169, 1) to (192, 1) memory blocks memory blocks memory blocks ujtag flashrom top row (7, 79) to (189, 79) bottom row (5, 78) to (192, 78) i/o tile (3, 77) (3, 76) memory blocks (3, 3) (3, 2) versatile (core) (3, 75) versatile (core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) versatile(core) (194, 75) versatile (core) (197, 79) (194, 77) (194, 76) i/o tile to analog block
fusion family of mixed signal fpgas revision 4 2-9 routing architecture the routing structure of fusion devices is designed to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources; effici ent long-line resources; high-speed very-long-line resources; and the high-performance versanet networks. the ultra-fast local resources are dedicated lines that allow the output of each versatile to connect directly to every input of the eight surrounding versatiles ( figure 2-8 ). the exception to this is that the set/clr input of a versatile configured as a d-flip-f lop is driven only by the versanet global network. the efficient long-line resources provide routing for longer distances and higher-fanout connections. these resources vary in length (spanning one, two, or four versatiles), run both vertically and horizontally, and cover the entire fusion device ( figure 2-9 on page 2-10 ). each versatile can drive signals onto the efficient long-line resources, whic h can access every input of every versatile. active buffers are inserted automatically by r outing software to limit loading effects. the high-speed very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets : length 12 versatiles in the vertical direction and length 16 in the horizontal direction from a given core versatile ( figure 2-10 on page 2-11 ). very long lines in fusion devices, like those in proasic3 devices, have been enh anced. this provides a significant performance boost for long-reach signals. the high-performance versanet global networks are lo w-skew, high-fanout nets that are accessible from external pins or from internal logic ( figure 2-11 on page 2-12 ). these nets are typically used to distribute clocks, reset signals, and other high-fanout nets requiring minimum skew. the versanet networks are implemented as clock trees, and signals can be introduced at any junction. these can be employed hierarchically, with signals accessing every input on all versatiles. note: input to the core cell for the d-flip-flop set and reset is only available via the versanet global network connection. figure 2-8 ? ultra-fast local lines connected to the eight nearest neighbors l l l l l l inputs output ultra-fast local lines (connects a versatile to the adjacent versatile, i/o buffer, or memory block) l ll long lines
device architecture 2-10 revision 4 figure 2-9 ? efficient long-line resources l l llll l lllll l l llll l l llll l l llll spans one versatile spans two versatiles spans four versatiles spans one versatile spans two versatiles spans four versatiles versatile
fusion family of mixed signal fpgas revision 4 2-11 figure 2-10 ? very-long-line resources high-speed, very-long-line resources pad ring pad ring i/o ring i/o ring 1612 block of versatiles sram
device architecture 2-12 revision 4 global resources (versanets) fusion devices offer powerful and flexible control of circuit timing through the use of analog circuitry. each chip has six cccs. the west ccc also contains a pll core. in the two larger devices (afs600 and afs1500), the west and the east cccs each cont ain a pll. the plls include delay lines, a phase shifter (0, 90, 180, 270), and clock multipliers/d ividers. each ccc has all the circuitry needed for the selection and interconnection of inputs to the ve rsanet global network. the east and west cccs each have access to three versanet global lines on each side of the chip (six lines total). the cccs at the four corners each have access to three quadrant gl obal lines on each quadrant of the chip. advantages of the versanet approach one of the architectural be nefits of fusion is the set of powerful and low-delay versanet global networks. fusion offers six chip (main) global networks that are distributed from the center of the fpga array ( figure 2-11 ). in addition, fusion devices have three regio nal globals (quadrant globals) in each of the four chip quadrants. each core versatile has a ccess to nine global network resources: three quadrant and six chip (main) global networks. there are a total of 18 global networks on the device. each of these networks contains spines and ribs that reach all versatiles in all quadrants ( figure 2-12 on page 2-13 ). this flexible versanet global network archit ecture allows users to map up to 180 different internal/external clocks in a fusion device. details on the versanet networks are given in table 2-4 on page 2-13 . the flexibility of the fusion versanet global network allows the designer to address several design requirements. user applications that are clo ck-resource-intensive can ea sily route external or gated internal clocks using versanet global rout ing networks. designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout net s to the versanet global network. figure 2-11 ? overview of fusion versanet global network main (chip) global network top spine bottom spine pad ring pad ring i/o ring i/o ring chip (main) global pads global pads high-performance versanet global network global spine global ribs spine-selection tree mux quadrant global pads
fusion family of mixed signal fpgas revision 4 2-13 figure 2-12 ? global network architecture table 2-4 ? globals/spines/rows by device afs090 afs250 afs600 afs1500 global versanets (trees)* 9 9 9 9 versanet spines/tree 4 8 12 20 total spines 36 72 108 180 versatiles in each top or bottom spine 384 768 1,152 1,920 total versatiles 2,304 6,144 13,824 38,400 note: *there are six chip (main) globals and three globals per quadrant. northwest quadrant global network southeast quadrant global network chip (main) global network 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc ccc ccc ccc ccc ccc
device architecture 2-14 revision 4 versanet global networks and spine access the fusion architecture contains a total of 18 segmented global networks that can access the versatiles, sram, and i/o tiles on the fusion device. there are 6 chip (main) global networks that access the entire device and 12 quadrant networks (3 in each quadrant). each device has a total of 18 globals. these versanet global networks offer fas t, low-skew routing resources for high-fanout nets, including clock signals. in addition, these highly segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 180 internal/external clocks (in an afs1500 device) or other high-fanout nets in fusion device s. optimal usage of these low-skew networks can result in significant improvement in design performance on fusion devices. the nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, wh ich has three spines, and the chip (main) global network, which has six spines. note that there are three quadrant sp ines in each quadrant of the device. there are four quadrant global network regions per device ( figure 2-12 on page 2-13 ). the spines are the vertical branches of the global network tree, shown in figure 2-11 on page 2-12 . each spine in a vertical column of a chip (main) global network is further divided into two equal-length spine segments: one in the top and one in the bottom half of the die. each spine and its associated ribs cover a certain area of the fusion device (the "scope" of the spine; see figure 2-11 on page 2-12 ). each spine is accessed by the dedicated global network mux tree architecture, which defines how a particular spine is driven?either by the signal on the global network from a ccc, for example, or anot her net defined by the user ( figure 2-13 ). quadrant spines can be driven from user i/os on the north and south sides of the die, via analog i/os configured as direct digital inputs. the ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design. details of the chip (main) global netwo rk spine-selection mux are presented in figure 2-13 . the spine drivers for each spine are located in the middle of the die. quadrant spines are driven from a north or south rib. access to the top and bottom ribs is from the corner ccc or from the i/os on the north and south sides of the device. for details on using spines in fusion devices, see the application note using global resources in actel fusion devices . figure 2-13 ? spine-selection mu x of global tree internal/external signal internal/external signal internal/external signals spine global rib global driver mux tree node mux tree node mux internal/external signals tree node mux
fusion family of mixed signal fpgas revision 4 2-15 clock aggregation clock aggregation allows for multi-spine clock domai ns. a mux tree provides the necessary flexibility to allow long lines or i/os to access dom ains of one, two, or four global spines. signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also through local resources in the north and south ribs, allowing i/os to feed dire ctly into the clock system. as figure 2-14 indicates, this access system is contiguous. there is no break in the middle of the chip for nort h and south i/o versanet acce ss. this is different from the quadrant clocks, located in these ribs, which only reach the middle of the rib. refer to the using global resources in actel fusion devices application note. figure 2-14 ? clock aggregation tree architecture global spine global rib global driver and mux i/o access internal signal access i/o tiles global signal access tree node mux
device architecture 2-16 revision 4 global resource characteristics afs600 versanet topology clock delays are device-specific. figure 2-15 is an example of a global tree used for clock routing. the global tree presented in figure 2-15 is driven by a ccc located on th e west side of the afs600 device. it is used to drive all d-flip-flops in the device. figure 2-15 ? example of global tree use in an afs600 device for clock routing central global rib versatile rows global spine ccc
fusion family of mixed signal fpgas revision 4 2-17 versanet timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these ar e dependent upon i/o standard, and the clock may be driven and conditioned internally by the ccc module. ta b l e 2 - 5 , table 2-6 , ta b l e 2 - 7 , and table 2-8 on page 2-18 present minimum and maximum global clock delays within the device minimum and maximum delays are measured with minimum and maximum loading, respectively. timing characteristics table 2-5 ? afs1500 global resource timing commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global cloc k 1.53 1.75 1.74 1.99 2.05 2.34 ns t rckh input high delay for global clo ck 1.53 1.79 1.75 2.04 2.05 2.40 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.29 0.34 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-6 ? afs600 global resource timing commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.27 1.49 1.44 1.70 1.69 2.00 ns t rckh input high delay for global clock 1.26 1.54 1.44 1.75 1.69 2.06 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.27 0.31 0.36 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-18 revision 4 table 2-7 ? afs250 global resource timing commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.89 1.12 1.02 1.27 1.20 1.50 ns t rckh input high delay for global clock 0.88 1.14 1.00 1.30 1.17 1.53 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.30 0.35 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-8 ? afs090 global resource timing commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.84 1.07 0.96 1.21 1.13 1.43 ns t rckh input high delay for global clock 0.83 1.10 0.95 1.25 1.12 1.47 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.27 0.30 0.36 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-19 clocking resources the fusion family has a robust collection of clocking peripherals, as shown in the block diagram in figure 2-16 . these on-chip resources enable the creation, manipulation, and distribution of many clock signals. the fusion integrated rc oscillator pr oduces a 100 mhz clock source with no external components. for systems requiring mo re precise clock signals, the fu sion family supports an on-chip crystal oscillator circuit. the integrated plls in each fusion device can use the rc oscillator, crystal oscillator, or another on-chip clock signal as a source . these plls offer a variety of capabilities to modify the clock source (multiply, divide, synchronize, advan ce, or delay). utilizing the ccc found in the popular proasic3 family, fusion incorporates six ccc blocks. the cccs allow access to fusion global and local clock distribution nets, as described in the "global resources (versanets)" section on page 2-12 . figure 2-16 ? fusion clocking options clock out to fpga core through ccc glint gndosc on-chip off-chip vccosc crystal oscillator clock i/os external crystal external rc xtal clock pll/ ccc gla to core clkout ngmux glc from fpga core 100 mhz rc oscillator or xtal1 xtal2
device architecture 2-20 revision 4 rc oscillator the rc oscillator is an on-chip free-running clock source generating a 100 mhz clock. it can be used as a source clock for both on-chip and off-chip resources. when used in conjunction with the fusion pll and ccc circuits, the rc oscillator clock source can be used to generate cl ocks of varying frequency and phase. the fusion rc oscillator is very accurate at 1% over commercial temperature ranges and and 3% over industrial temperature ranges. it is an automated clock, requirin g no setup or configuration by the user. it requires only that the power and gndosc pins be connected; no external components are required. the rc oscillator can be used to dr ive either a pll or another internal signal. rc oscillator characteristics table 2-9 ? electrical characteristics of rc oscillator parameter description conditions min. typ. max. units f rc operating frequency 100 mhz accuracy temperature: 0c to 85c voltage: 3.3 v 5% 1% temperature: ?40c to 125c voltage: 3.3 v 5% 3% output jitter period ji tter (at 5 k cycles) 100 ps cycle?cycle jitter (at 5 k cycles) 100 ps period jitter (at 5 k cycles) with 1 khz / 300 mv peak-to-peak noise on power supply 150 ps cycle?cycle jitter (at 5 k cycles) with 1 khz / 300 mv peak-to-peak noise on power supply 150 ps output duty cycle 50 % i dynrc operating current 1 ma
fusion family of mixed signal fpgas revision 4 2-21 crystal oscillator the crystal oscillator (xtlosc) is source that generates the clock fr om an external crystal. the output of xtlosc clkout signal can be selected as an input to the pll. refer to the "clock conditioning circuits" section for more details. the xtlosc can operate in normal operations and standby mode (rtc is running and 1.5 v is not present). in normal operation, the internal fpga_en signal is '1' as long as 1.5 v is present for vcc. as such, the internal enable signal, xtl_en, for crystal osci llator is enabled since fpga_en is asserted. the xtl_mode has the option of using mode or rtc_mode, depending on selmode. during standby, 1.5 v is not available, as such, and fpga_en is '0'. selmode must be asserted in order for xtl_en to be enabled; hence xtl_mode relies on rtc_mode. selmode and rtc_mode must be connected to rtcxtlsel and rtcxtlmode from the ab respectively for correct operation during standby (refer to the "real-time counter system" section on page 2-33 for a detailed description). the crystal oscillator can be configured in one of four modes: ? rc network, 32 khz to 4 mhz ? low gain, 32 to 200 khz ? medium gain, 0.20 to 2.0 mhz ? high gain, 2.0 to 20.0 mhz in rc network mode, the xtal1 pin is c onnected to an rc circuit, as shown in figure 2-16 on page 2-19 . the xtal2 pin should be left floating. the rc value can be chosen based on figure 2-18 for any desired frequency between 32 khz and 4 mhz. the rc network mode can also accommodate an external clock source on xtal1 instead of an rc circuit. in low gain, medium gain, and high gain, an external crystal component or ceramic resonator can be added onto xtal1 and xtal2, as shown in figure 2-16 on page 2-19 . in the case where the crystal oscillator block is not used, the xtal1 pin should be connected to gnd and the xtal2 pin should be left floating. note: *internal signal?does not exist in macro. figure 2-17 ? xtlosc macro xtlosc clkout xtl 0 1 mode[1:0] rtc_mode[1:0] selmode fpga_en* xtl_en* xtl_mode*
device architecture 2-22 revision 4 figure 2-18 ? crystal oscillator: rc time consta nt values vs. frequency (typical) table 2-10 ? xtlosc signals descriptions signal name width direction function xtl_en* 1 enables the crystal. active high. xtl_mode* 2 settings for the crystal clock for different frequency. value modes frequency range b'00 rc network 32 khz to 4 mhz b'01 low gain 32 to 200 khz b'10 medium gain 0.20 to 2.0 mhz b'11 high gain 2.0 to 20.0 mhz selmode 1 in selects the source of xtl_mode and also enables the xtl_en. connect from rtcxtlsel from ab. 0 for normal operation or sleep mode, xtl_en depends on fpga_en, xtl_mode depends on mode 1 for standby mode, xtl_en is enabled, xtl_mode depends on rtc_mode rtc_mode[1:0] 2 in settings for the crystal clock for different frequency ranges. xtl_mode uses rtc_mode when selmode is '1'. mode[1:0] 2 in settings for the crystal clock for different frequency ranges. xtl_mode uses mode when selmode is '0'. in standby, mode inputs will be 0's. fpga_en* 1 in 0 when 1.5 v is not pres ent for vcc 1 when 1.5 v is present for vcc xtl 1 in crystal clock source clkout 1 out crystal clock output note: *internal signal?does not exist in macro. 0.0 1.00e-0.7 1.00e-0.6 1.00e-0.5 1.00e-0.4 1.00e-0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 rc time constant (sec) frequency (mhz) rc time constant values vs. frequency
fusion family of mixed signal fpgas revision 4 2-23 clock conditioning circuits in fusion devices, the cccs are used to implement frequency division, frequency multiplication, phase shifting, and delay operations. the cccs are available in six chip locations?each of the four chip corners and the middle of the east and west chip sides. each ccc can implement up to three independent gl obal buffers (with or wi thout programmable delay), or a pll function (programmable frequency division/multi plication, phase shift, and delays) with up to three global outputs. unused global outputs of a pll can be used to implement independent global buffers, up to a maximum of three global outputs for a given ccc. a global buffer can be placed in any of the three global locations (clka-gla, clkb-glb, and clkc- glc) of a given ccc. a pll macro uses the clka ccc input to drive its refe rence clock. it uses the gla and, optionally, the glb and glc global outputs to drive the global networks. a pll macro can also drive the yb and yc regular core outputs. the glb (or glc) global output cannot be reused if the yb (or yc) output is used ( figure 2-19 ). refer to the "pll macro" section on page 2-29 for more information. each global buffer, as well as the pll referenc e clock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core the ccc block is fully configurable, either via flash configuration bits set in the programming bitstream or through an asynchronous interface. this asynchronous interface is dynamically accessible from inside the fusion device to permit changes of parameters (such as divide ratios) during device operation. to increase the versatility and flexibility of t he clock conditioning system, the ccc configuration is determined either by the user during the design proc ess, with configuration data being stored in flash memory as part of the device prog ramming procedure, or by writing data into a dedicated shift register during normal device operation. this latter mode a llows the user to dynamic ally reconfigure the ccc without the need for core programming. the shift regist er is accessed through a simple serial interface. refer to the "ujtag applications in microsemi?s low-power flash devices" chapter of the fusion fpga fabric user?s guide and the "ccc and pll characteristics" section on page 2-30 for more information.
device architecture 2-24 revision 4 notes: 1. visit the microsemi soc products group website for application notes concerning dynamic pll reconfiguration. refer to the "pll macro" section on page 2-29 for signal descriptions. 2. many specific inbuf macros support the wide variety of single-ended and differential i/o standards for the fusion family. 3. refer to the igloo, proasic3, smartfusion and fusion macro library guide for more information. figure 2-19 ? fusion ccc options: global buffers with the pll macro table 2-11 ? available selections of i/o standards wi thin clkbuf and cl kbuf_lvds/lvpecl macros clkbuf macros clkbuf_lvcmos5 clkbuf_lvcmos33 1 clkbuf_lvcmos18 clkbuf_lvcmos15 clkbuf_pci clkbuf_lvds 2 clkbuf_lvpecl notes: 1. this is the default macro. for more details, refer to the igloo, proasic3, smartfusion and fusion macro library guide . 2. the b-lvds and m-lvds standards are suppor ted with clkbuf_lvds. padn padp y pad y input lvds/lvpecl macro inbuf 2 macro gla or gla and (glb or yb) or gla and (glc or yc) or gla and (glb or yb) and (glc or yc) clock source clock conditioning output oadivhalf oadiv[4:0] oamux[2:0] dlygla[4:0] obdiv[4:0] obmux[2:0] dlyyb[4:0] dlyglb[4:0] ocdiv[4:0] ocmux[2:0] dlyyc[4:0] dlyglc[4:0] findiv[6:0] fbdiv[6:0] fbdly[4:0] fbsel[1:0] xdlysel vcosel[2:0] clka extfb powerdown oadivrst gla lock glb yb glc yc
fusion family of mixed signal fpgas revision 4 2-25 global buffers with no programmable delays the clkbuf and clkbuf_lvpecl/lvds macros are co mposite macros that include an i/o macro driving a global buffer, hardwired together ( figure 2-20 ). the clkint macro provides a global buffe r function driven by the fpga core. the clkbuf, clkbuf_lvpecl/lvds, and clkint macros are pass-th rough clock sources and do not use the pll or provide any pr ogrammable delay functionality. many specific clkbuf macros s upport the wide variety of single-ended and differential i/o standards supported by fusion devices. the available clkbuf macros are described in the igloo, proasic3, smartfusion and fusion macro library guide . figure 2-20 ? global buffers with no programmable delay clkbuf_lvds/lvpecl macro padn padp yy a pad y clkint macro clkbuf macro gla or glb or glc clock source clock conditioning output none
device architecture 2-26 revision 4 global buffers with programmable delay the clkdly macro is a pass-through clock source that does not use the pll, but provides the ability to delay the clock input using a programmable delay ( figure 2-21 ). the clkdly macro takes the selected clock input and adds a user-defined delay element. this macro generates an output clock phase shift from the input clock. the clkdly macro can be driven by an inbuf ma cro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. many specific inbuf macros support the wide variet y of single-ended and differential i/o standards supported by the fusion family. the available inbuf macros are described in the igloo, proasic3, smartfusion and fusion macro library guide. the clkdly macro can be driven directly from the fpga core. the clkdly macro can also be driven from an i/o that is routed through the fpga regular routing fabric. in this case, users must instantiate a specia l macro, pllint, to differentiate from the hardwired i/o connection described earlier. the visual clkdly configuration in the smartgen part of the libero soc and designer tools allows the user to select the desired amount of delay and co nfigures the delay elements appropriately. smartgen also allows the user to select the input clock sour ce. smartgen will automatically instantiate the special macro, pllint, when needed. figure 2-21 ? fusion ccc options: global bu ffers with programmable delay padn padp y pad y input lvds/lvpecl macro inbuf* macro gla or glb or glc clock source clock conditioning output clk dlygl[4:0] gl
fusion family of mixed signal fpgas revision 4 2-27 global input selections each global buffer, as well as the pll reference clock, can be driven from one of the following ( figure 2- 22 ): ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core notes: 1. represents the global input pins. globals have direct access to the clock conditioning block and are not routed via the fpga fabric. refer to the "user i/o naming convention" section on page 2-161 for more information. 2. instantiate the routed clock source input as follows: a) connect the output of a logic element to the cl ock input of the pll, clkdly, or clkint macro. b) do not place a clock source i/o (inbuf or inbuf_lvpecl/lvds) in a relevant global pin location. 3. lvds-based clock sources are available in the east and west banks on all fusion devices. figure 2-22 ? clock input sources including clkbu f, clkbuf_lvds/l vpecl, and clkint + + source for ccc (clka or clkb or clkc) each shaded box represents an input buffer called out by the appropriate name: inbuf or inbuf_lvds/lvpecl. to core routed clock (from fpga core) 2 sample pin names gaa0 1 gaa1 1 gaa2 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source.
device architecture 2-28 revision 4 ccc physical implementation the ccc circuit is composed of the following ( figure 2-23 ): ? pll core ? 3 phase selectors ? 6 programmable delays and 1 fixed delay ? 5 programmable frequency dividers that provid e frequency multiplication/division (not shown in figure 2-23 because they are automati cally configured based on the user's required frequencies) ? 1 dynamic shift register that provides ccc dynamic reconfiguration capability (not shown) ccc programming the ccc block is fully configurable. it is configured via static flash configuration bits in the array, set by the user in the programming bitstream, or configured through an asynchronous dedicated shift register, dynamically accessible from inside the fusion devic e. the dedicated shift register permits changes of parameters such as pll divide ratios and delays during device operation. this latter mode allows the user to dynamically reconfigure the pll without th e need for core programming. the register file is accessed through a simple serial interface. note: clock divider and multiplier blocks are not s hown in this figure or in smartgen. they are automatically configured based on the user's required frequencies. figure 2-23 ? pll block pll core phase select phase select phase select gla clka glb yb glc yc fixed delay programmable delay type 1 programmable delay type 2 programmable delay type 2 programmable delay type 1 programmable delay type 2 programmable delay type 1 four-phase output
fusion family of mixed signal fpgas revision 4 2-29 pll macro the pll functionality of the clock conditioning block is supported by the pll ma cro. note that the pll macro reference clock uses the clka input of the ccc block, which is only accessible from the global a[2:0] package pins. refer to figure 2-22 on page 2-27 for more information. the pll macro provides five derived clocks (three i ndependent) from a single reference clock. the pll feedback loop can be driven either internally or externally. the pll macro also provides power-down input and lock output signals. during power-up, powerdown should be asserted low until vcc is up. see figure 2-19 on page 2-24 for more information. inputs: ? clka: selected clock input ? powerdown (active low): disables plls. the default state is power-down on (active low). outputs: ? lock (active high): indicates that pll out put has locked on the input reference signal ? gla, glb, glc: outputs to respective global networks ? yb, yc: allows output from the ccc to be routed back to the fpga core as previously described, the pll allows up to five flexible and independently configurable clock outputs. figure 2-23 on page 2-28 illustrates the various clock output options and delay elements. as illustrated, the pll supports three distinct output frequencies from a given input clock. two of these (glb and glc) can be routed to the b and c global networks, respectively, and/or routed to the device core (yb and yc). there are five delay elements to support phase contro l on all five outputs (gla, glb, glc, yb, and yc). there is also a delay element in the feedback loop that can be used to advance the clock relative to the reference clock. the pll macro reference clock can be driven by an inbuf macro to create a composite macro, where the i/o macro drives the global buffer (with programma ble delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. the pll macro reference clock can be dr iven directly from the fpga core. the pll macro reference clock can also be driven fr om an i/o routed through the fpga regular routing fabric. in this case, users must instantiate a special macro, pllint, to differentiate it from the hardwired i/o connection described earlier. the visual pll configuration in smartgen, available with the libero soc and designer tools, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. smartgen a llows the user to select the various delays and phase shift values necessary to adjust the phases between the refe rence clock (clka) and the derived clocks (gla, glb, glc, yb, and yc). smartgen also allows the user to select where the inpu t clock is coming from. smartgen automatically inst antiates the special macro, pllint, when needed.
device architecture 2-30 revision 4 ccc and pll ch aracteristics timing characteristics table 2-12 ? fusion ccc/pll specification parameter min. typ. max. unit clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz delay increments in programmable delay blocks 1, 2 160 3 ps number of programmable values in each programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-peak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 1.00% 1.00% 24 mhz to 100 mhz 1.50% 1.50% 100 mhz to 250 mhz 2.25% 2.25% 250 mhz to 350 mhz 3.50% 3.50% acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 4 lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 0.6 5.56 ns delay range in block: programmable delay 2 1, 2 0.025 5.56 ns delay range in block: fixed delay 1, 2 2.2 ns notes: 1. this delay is a function of voltage and temperature. see table 3-7 on page 3-9 for deratings. 2. t j = 25c, vcc = 1.5 v 3. when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available. refer to the libero soc online help associated with the core for more information. 4. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by period jitter parameter.
fusion family of mixed signal fpgas revision 4 2-31 no-glitch mux (ngmux) positioned downstream from the pll/ccc blocks, th e ngmux provides a special switching sequence between two asynchronous clock domains that prev ents generating any unwanted narrow clock pulses. the ngmux is used to switch the source of a gl obal between three different clock sources. allowable inputs are either two pll/ccc outputs or a pll/ ccc output and a regular net, as shown in figure 2-24 . the glmuxcfg[1:0] configuration bits determine the source of the clk inputs (i.e., internal signal or glc). these are set by smartgen during design but ca n also be changed by dynamically reconfiguring the pll. the glmuxsel[1:0] bits contro l which clock source is passed thr ough the ngmux to the global network (gl). see table 2-13 . figure 2-24 ? ngmux table 2-13 ? ngmux configuration and selection table glmuxcfg[1:0] glmuxsel[1:0] selected input signal mux type 00 x 0 gla 2-to-1 glmux x1glc 01 x 0 gla 2-to-1 glmux x 1 glint crystal oscillator rc oscillator w i/o ring ccc/pll clock i/os from fpga core pll/ ccc glint gla glc ngmux glmuxcfg[1:0] pwr up glmuxsel[1:0] gl to clock rib driver
device architecture 2-32 revision 4 the ngmux macro is simplified to show the two clock options that have been selected by the glmuxcfg[1:0] bits. figure 2-25 illustrates the ngmux macro. duri ng design, the two clock sources are connected to clk0 and clk1 and are controlled by glmuxsel[1:0] to determine which signal is to be passed through the mux. the sequence of switching between two clock sources (from clk0 to clk1) is as follows ( figure 2-26 ): ? glmuxsel[1:0] transitions to initiate a switch. ? gl drives one last complete clk0 positive pulse (i.e., one rising edge followed by one falling edge). ? from that point, gl stays low until t he second rising edge of clk1 occurs. ? at the second clk1 rising edge, gl will begin to continuously deliver the clk1 signal. ? minimum t sw = 0.05 ns at 25c (typical conditions) for examples of ngmux operation, refer to the fusion fpga fabric user?s guide . figure 2-25 ? ngmux macro figure 2-26 ? ngmux waveform clk0 clk1 g l glmuxsel[1:0] clk0 clk1 glmuxsel[1:0] gl t sw
fusion family of mixed signal fpgas revision 4 2-33 real-time counter system the rtc system enables fusion devices to support standby and sleep modes of operation to reduce power consumption in many applications. ? sleep mode, typical 10 a ? standby mode (rtc running), typical 3 ma with 20 mhz the rtc system is comp osed of five cores: ? rtc sub-block inside analog block (ab) ? voltage regulator and power system monitor (vrpsm) ? crystal oscillator (xtlosc); refer to the "c rystal oscillator" section in the fusion clock resources chapter of the fusion fpga fabric user?s guide for more detail. ? crystal clock; does not require instantiation in rtl ? 1.5 v voltage regulator; does not require instantiation in rtl all cores are powered by 3.3 v supplies, so the rt c system is operational without a 1.5 v supply during standby mode. figure 2-27 shows their connection. notes: 1. signals are hardwired internally and do not exist in the macro core. 2. user is only required to instantiate the vrpsm macro if the us er wishes to specify pupo behavior of the voltage regulator to be different from the default, or employ us er logic to shut the voltage regulator off. figure 2-27 ? real-time counter system (not all the signals are shown for the ab macro) vrpu ptbase 1 ptem 1 pub vrinitstate rtcpsmmatch fpgagood pucore vren 1 vren 1 vrpsm 1.5 voltage regulator rtcxtlsel rtcmatch rtcpsmmatch xtlosc real-time counter xtal1 xtal2 clkout rtc_mode[1:0] selmode rtcclk external pass transistor 2n2222 3.3 v power-up/-down toggle control switch 1.5 v trst 1 external pin internal pin can be route to pll rtcxtlmode[1:0] cores do not require any rtl instantiation cores require rtl instantiation 2 sub-block in cores does not require additional rtl instantiation xtl xtl 1 crystal clock mode[1:0] fpga_en 1 ab
device architecture 2-34 revision 4 modes of operation standby mode standby mode allows periodic power-up and power-down of the fpga fabric. in standby mode, the real- time counter and crystal block are on. the fpga is not powered by disabling the 1.5 v voltage regulator. the 1.5 v voltage regulator can be enabled when the preset count is matched. refer to the "real-time counter (part of ab macro)" section for details. to enter standby mode, the rtc must be first configured and enabled. then vrpsm is shut off by deasserting the vrpu signal. the 1.5 v voltage regulator is then disabled, and shuts off the 1.5 v output. sleep mode in sleep mode, the real-time counte r and crystal blocks are off. the 1. 5 v voltage regulator inside the vrpsm can only be enabled by the pub or trst pin. refer to the "voltage regulator and power system monitor (vrpsm)" section on page 2-37 for details on power-up and power-down of the 1.5 v voltage regulator. standby and sleep mode circuit implementation for extra power savings, vjtag and vpump should be at the same voltage as vcc, floated or ground, during standby and sleep modes. note that when vj tag is not powered, the 1.5 v voltage regulator cannot be enabled through trst. vpump and vjtag can be controlled through an external switch. microsemi recommends adg839, adg849, or adg841 as possible switches. figure 2-28 shows the implementation for controlling vpump. the in signal of the switch can be connected to ptbase of the fusion device. vjtag can be controlled in same manner. figure 2-28 ? implementation to control vpump ptbase ptem external pass transistor 2n2222 3.3 v 1.5 v vpump (or jtag) pin of fusion vpump (or jtag) supply fusion adg841 s in
fusion family of mixed signal fpgas revision 4 2-35 real-time counter (part of ab macro) the rtc is a 40-bit loadable counter and used as the primary timekeeping element ( figure 2-29 ). the clock source, rtcclk, must come from the clkout signal of the crystal oscillator. the rtc can be configured to reset itself when a count value r eaches the match value set in the match register. the rtc is part of the analog block (ab) macro. the rtc is configured by the analog configuration mux (acm). each address contains one byte of data. the circuitry in the rtc is powered by vcc33a, so the rtc can be used in standby mode when the 1.5 v supply is not present. the 40-bit counter can be preloaded with an initial va lue as a starting point by the counter register. the count from the 40-bit counter can be read through the same set of address space. the count comes from a read-hold register to avoid data changing during read. when the counter value equals the match register value, all match bits register values will be 0xffffffffff. the rtcmatch and rtcpsmmatch signals will assert. the 40-bit counter can be configured to automatically reset to 0x0000000000 when the counter value equals the match register value. the automatic reset does not apply if the match register value is 0x0000000000. the rtcclk has a prescaler to divide the clock by 128 before it is used for the 40-bit counter. below is an example of how to calculate the off time. figure 2-29 ? rtc block diagram table 2-14 ? rtc signal description signal name width direction function rtcclk 1 in must come from clkout of xtlosc. rtcxtlmode[1:0] 2 out controlled by xt_mode in ctrl_stat. signal must connect to the rtc_mode signal in xtlosc, as shown in figure 2-27 . rtcxtlsel 1 out controlled by xtal_en from ctrl_stat register. signal must connect to rtc_mode signal in xtlosc in figure 2-27 . rtcmatch 1 out match signal for fpga 0 ? counter value does not equal the match register value. 1 ? counter value equals the match register value. rtcpsmmatch 1 out same signal as rtcmatch. signal must connect to rtcpsmmatch in vrpsm, as shown in figure 2-27 . xt_mode[1:0] rtcmatch rtcpsmmatch rtcclk acm registers 1.5 v to 3.3 v level shifter control status 40-bit counter match reg matchbits reg counter reg counter read-hold reg real-time counter crystal prescaler f rtcclk divide by 128 xtal_en rtcxtlsel rtcxtlmode[1:0]
device architecture 2-36 revision 4 example: calculation for match count to put the fusion device on standby for one hour using an external crystal of 32.768 khz: the period of the crystal oscillator is t crystal : t crystal = 1 / 32.768 khz = 30.518 s the period of the counter is t counter : t counter = 30.518 us x 128 = 3.90625 ms the match count for 1 hour is ? tmatch: ? tmatch / t counter = (1 hr x 60 min/hr x 60 sec/min) / 3.90625 ms = 921600 or 0xe1000 using a 32.768 khz crystal, the maximum standby ti me of the 40-bit counter is 4,294,967,296 seconds, which is 136 years. table 2-16 ? rtc control/st atus register bit name description default value 7 rtc_rst rtc reset 1 ? resets the rtc 0 ? deassert reset on after two acm_clk cycle. 6 cntr_en counter enable 1 ? enables the counter; rtc_rst must be deasserted as well. first counter increments after 64 rtcclk positive edges. 0 ? disables the crystal prescaler but does not reset the counter value. counter value can only be updated when the counter is disabled. 0 5 vr_en_mat voltage regulator enable on match 1 ? enables rtcmatch and rtcpsmmatch to output 1 when the counter value equals the match regist er value. this enables the 1.5 v voltage regulator when rtcpsmmatch connects to the rtcpsmmatch signal in vrpsm. 0 ? rtcmatch and rtcpsmmatch output 0 at all times. 0 4:3 xt_mode[1:0] crystal mode controls rtcxtlmode[1:0]. c onnects to rtc_mode signal in xtlosc. xtl_mode uses this value when xtal_en is 1. see the "crystal oscillator" section on page 2-21 for mode configuration. 00 2 rst_cnt_omat reset counter on match 1 ? enables the sync clear of the counter when the counter value equals the match register value. the counter clears on the rising edge of the clock. if all the match registers are set to 0, the clear is disabled. 0 ? counter increments indefinitely 0 1 rstb_cnt counter reset, active low 0 - resets the 40-bit counter value 0 0 xtal_en crystal enable controls rtcxtlsel. connects to selmode signal in xtlosc. 0 ? xtlosc enables control by fpga_en; xt_mode is not used. sleep mode requires this bit to equal 0. 1 ? enables xtlosc, xtl_mode control by xt_mode standby mode requires this bit to be set to 1. see the "crystal oscillator" section on page 2-21 for further details on selmode configuration. 0
fusion family of mixed signal fpgas revision 4 2-37 voltage regulator and powe r system monitor (vrpsm) the vrpsm macro controls the power-up state of the fpga. the power-up bar (pub) pin can turn on the voltage regulator when set to 0. trst can en able the voltage regulator wh en deasserted, allowing the fpga to power-up when user want access to jtag ports. the inputs vrinitstate and rtcpsmmatch come from the flash bits a nd rtc, and can also power up the fpga. table 2-15 ? memory map for rtc in acm register and description acmaddr register name description use default value 0x40 counter0 counter bits 7:0 u sed to preload the counter to a specified start point. 0x00 0x41 counter1 counter bits 15:8 0x00 0x42 counter2 counter bits 23:16 0x00 0x43 counter3 counter bits 31:24 0x00 0x44 counter4 counter bits 39:32 0x00 0x48 matchreg0 match register bits 7:0 the rtc comparison bits 0x00 0x49 matchreg1 match register bits 15:8 0x00 0x4a matchreg2 match register bits 23:16 0x00 0x4b matchreg3 match register bits 31:24 0x00 0x4c matchreg4 match register bits 39:32 0x00 0x50 matchbit0 individual match bits 7:0 the output of the xnor gates 0 ? not matched 1 ? matched 0x00 0x51 matchbit1 individual match bits 15:8 0x00 0x52 matchbit2 individual match bits 23:16 0x00 0x53 matchbit3 individual match bits 31:24 0x00 0x54 matchbit4 individual match bits 29:32 0x00 0x58 ctrl_stat control (write/read) / status (read only) register bits refer to table 2-16 on page 2-36 for details. 0x00 note: *signals are hardwired internally and do not exist in the macro core. figure 2-30 ? vrpsm macro vrpu pub vrinitstate rtcpsmmatch fpgagood pucore vren* vrpsm trst*
device architecture 2-38 revision 4 table 2-17 ? vrpsm signal descriptions signal name width dir. function vrpu 1 in voltage regulator power-up 0 ? voltage regulator disabled. pub must be floated or pulled up, and the trst pin must be grounded to disable the voltage regulator. 1 ? voltage regulator enabled vrinitstate 1 in voltage regulator initial state defines the voltage regulator status upon power-up of the 3.3 v. the signal is configured by libero soc when the vrpsm macro is generated. tie off to 1 ? voltage regulator enables when 3.3 v is powered. tie off to 0 ? voltage regulator disables when 3.3 v is powered. rtcpsmmatch 1 in rtc power system management match connect from rtcpsmatch signal from rtc in ab 0 transition to 1 turns on the voltage regulator pub 1 in external pin, built-in weak pull-up power-up bar 0 ? enables voltage regulator at all times trst* 1 in external pin, jtag test reset 1 ? enables voltage regulator at all times fpgagood 1 out indicator that the fpga is powered and functional no need to connect if it is not used. 1 ? indicates that the fpga is powered up and functional. 0 ? not possible to read by fpga since it has already powered off. pucore 1 out power-up core inverted signal of pub. no need to connect if it is not used. vren* 1 out voltage regulator enable connected to 1.5 v voltage regulat or in fusion device internally. 0 ? voltage regulator disables 1 ? voltage regulator enables note: *signals are hardwired internally and do not exist in the macro core.
fusion family of mixed signal fpgas revision 4 2-39 when trst is 1 or pub is 0, the 1.5 v voltage regulator is always on, putting the fusion device in normal operation at all times. ther efore, when the jtag po rt is not in reset, the fusion device cannot enter sleep mode or standby mode. to enter standby mode, the fusion device must fi rst power-up into normal operation. the rtc is enabled through the rtc control/status register described in the "real-time counter (part of ab macro)" section on page 2-35 . a match value corresponding to the wa ke-up time is loaded into the match register. the 1.5 v voltage regulator is disabled by setting vrpu to 0 to allow the fusion device to enter standby mode, when the 1.5 v supply is off but the rtc remains on. note: * to enter and exit standby mode without any external stimulus on pub or trst, the vr_en_mat in the ctrl_stat register must also be set to 1, so that rtcpsmmatch will assert when a match occurs; hence the device exits standby mode. figure 2-31 ? state diagram for all different power modes normal operation 3.3 v on, vren enable standby mode 3.3 v on, rtc enabled vren disabled off state 3.3 v off, pub pull-up, trst pull-down, vren disabled vrpu = 0 and pub = 1 and trst = 0 pub = 0 or trst = 1 vrpu = 0 and pub = 1 and trst = 0 and *rtc: ctrl_stat: xtal_en = 1 *rtcpsmmatch = 1 or pub = 0 or trst = 1 sleep mode 3.3 v on, vren disabled 3.3 v on, 1.5 v on (vr on) 3.3 v off 3.3 v on 3.3 v power supply on/off vinitstate = 0 and pub = 1 and trst = 0 vrinitstate = 1 or pub = 0 or trst = 1
device architecture 2-40 revision 4 1.5 v voltage regulator the 1.5 v voltage regulator uses an external pass tran sistor to generate 1.5 v from a 3.3 v supply. the base of the pass transistor is tied to ptbase, the collector is tied to 3.3 v, and an emitter is tied to ptbase and the 1.5 v supplies of the fusion device. figure 2-27 on page 2-33 shows the hook-up of the 1.5 v voltage regulator to an external pass transistor. microsemi recommends using a pn2222a or 2n2222a transistor. the gain of such a transistor is approximately 25, with a maximum base current of 20 ma. the maximum current that can be supported is 0.5 a. transistors with different gain can al so be used for different current requirements. table 2-18 ? electrical characteristics vcc33a = 3.3 v symbol parameter conditi on min typical max units vout output voltage tj = 25oc 1.425 1.5 1.575 v icc33a operation current tj = 25oc iload = 1 ma iload = 100 ma iload = 0.5 a 11 11 30 ma ma ma ? vout load regulation tj = 25oc iload = 1 ma to 0.5 a 90 mv ? vout line regulation tj = 25oc vcc33a = 2.97 v to 3.63 v iload = 1 ma vcc33a = 2.97 v to 3.63 v iload = 100 ma vcc33a = 2.97 v to 3.63 v iload = 500 ma 10.6 12.1 10.6 mv/v mv/v mv/v dropout voltage* tj = 25oc iload = 1 ma iload = 100 ma iload = 0.5 a 0.63 0.84 1.35 v v v iptbas e ptbase current tj = 25oc iload = 1 ma iload = 100 ma iload = 0.5 a 48 736 12 20 a a ma note: *data collected with 2n2222a.
fusion family of mixed signal fpgas revision 4 2-41 embedded memories fusion devices include four types of embedded me mory: flash block, flashrom, sram, and fifo. flash memory block fusion is the first fpga that offers a flash memory bl ock (fb). each fb block st ores 2 mbits of data. the flash memory block macro is illustrated in figure 2-32 . the port pin name and descriptions are detailed on table 2-19 on page 2-42 . all flash memory block signals are active high, except for clk and active low reset. all flash memory operations are synchron ous to the rising edge of clk. figure 2-32 ? flash memory block addr[17:0] wd[31:0] program clk reset rd[31:0] busy status[1:0] unprotectpage discardpage overwriteprotect pagelossprotect datawidth[1:0] ren wen erasepage sparepage auxblock readnext overwritepage pagestatus pipe lockrequest
device architecture 2-42 revision 4 flash memory block pin names table 2-19 ? flash memory block pin names interface name width direction description addr[17:0] 18 in byte offset into the fb. byte-based address. auxblock 1 in when asserted, the page addressed is used to access the auxiliary block within that page. busy 1 out when asserted, indicates that the fb is performing an operation. clk 1 in user interface clock. all operations and status are synchronous to the rising edge of this clock. datawidth[1:0] 2 in data width 00 = 1 byte in rd/wd[7:0] 01 = 2 bytes in rd/wd[15:0] 1x = 4 bytes in rd/wd[31:0] discardpage 1 in when asserted, the contents of the page buffer are discarded so that a new page write can be started. erasepage 1 in when asserted, the address page is to be programmed with all zeros. erasepage must transition synchron ously with the rising edge of clk. lockrequest 1 in when asserted, indicates to the jtag controller that the fpga interface is accessing the fb. overwritepage 1 in when asserted, the page addressed is overwritten with the contents of the page buffer if the page is writable. overwriteprotect 1 in when asserted, all program operations will set the overwrite protect bit of the page being programmed. pagestatus 1 in when asserted with ren, initiates a read page status operation. pagelossprotect 1 in when asse rted, a modified page buff er must be programmed or discarded before accessing a new page. pipe 1 in adds a pipeline stage to the output for operation above 50 mhz. program 1 in when asserted, writes the contents of the page buffer into the fb page addressed. rd[31:0] 32 out read data; data will be valid from the first non-busy cycle (busy = 0) after ren has been asserted. readnext 1 in when asserted with ren, initiates a read-next operation. ren 1 in when asserted, initiates a read operation. reset 1 in when asserted, resets the state of the fb (active low). sparepage 1 in when asserted, the sector addressed is used to access the spare page within that sector.
fusion family of mixed signal fpgas revision 4 2-43 all flash memory block input signals are active high, except for reset. status[1:0] 2 out status of the last operation completed: 00: successfu l completion 01: read-/unprotect-page: single error detected and corrected write: operation addressed a write-protected page erase-page: protection violation program: page buffer is unmodified protection violation 10: read-/unprotect-page: two or more errors detected 11: write: attempt to write to another page before programming current page erase-page/program: page write count has exceeded the 10-year retention threshold unprotectpage 1 in when asserted, the page addressed is copied into the page buffer and the page buffer is made writable. wd[31:0] 32 in write data wen 1 in when asserted, stores wd in the page buffer. table 2-19 ? flash memory block pin names (continued) interface name width direction description
device architecture 2-44 revision 4 flash memory block diagram a simplified diagram of the flash memory block is shown in figure 2-33 . the logic consists of the following sub-blocks: ? flash array contains all stored data. the flash array contains 64 sectors, and each sector contains 33 pages of data. ? page buffer a page-wide volatile register. a page contains 8 blocks of data and an aux block. ? block buffer contains the contents of the last block accessed. a block contains 128 data bits. ? ecc logic the fb stores error correction information with each block to perform single -bit error correction and double-bit error detection on all data blocks. figure 2-33 ? flash memory block diagram adddr[17:0] datawidth[1:0] ren readnext pagestatus wen erasepage program sparepage auxblock unprotectpage overwritepage discardpage overwriteprotect pagelossprotect pipe lockrequest clk reset status[1:0] busy control logic output mux block buffer (128 bits) ecc logic flash array = 64 sectors rd[31:0] wd[31 :0] page buffer = 8 blocks plus aux block
fusion family of mixed signal fpgas revision 4 2-45 flash memory block addressing figure 2-34 shows a graphical representation of the flash memory block. each fb is partitioned into sector s, pages, blocks, and bytes. there are 64 sectors in an fb, and each sector contains 32 pages and 1 spare page. each page contains 8 data blocks and 1 auxiliary block. each data block contains 16 bytes of user data, and the auxiliary block contains 4 bytes of user data. addressing for the fb is shown in table 2-20 . when the spare page of a sector is addressed (sparepage active), addr[11:7] are ignored. when the auxiliary block is addressed (a uxblock active), addr[6:2] are ignored. note: the spare page of sector 0 is unavailable for any user data. writes to this page will return an error, and reads will return all zeroes. figure 2-34 ? flash memory block organization byte 0 byte 1 byte 2 byte 3 byte 14 byte 15 block organization user data (32 bits) 140 block 0 1234567 aux block . . . . . . . . sector 0 sector 1 sector n . . . . 33 pages pag e 0 pag e 1 pag e 2 pag e 3 pag e 31 spare pag e 1190 notes: 1 block = 128 bits 1 page = 8 blocks plus the aux block 1 sector = 33 pages 1 flash array = 64 sectors table 2-20 ? fb address bit allocation addr[17:0] 17121176430 sector page block byte
device architecture 2-46 revision 4 data operations are performed in widths of 1 to 4 by tes. a write to a location in a page that is not already in the page buffer will cause the page to be read fr om the fb array and stored in the page buffer. the block that was addressed during the write will be put into the block buffer, and the data written by wd will overwrite the data in the block buffer. after the data is written to the block buffer, the block buffer is then written to the page buffer to keep both buffers in sync. subsequent writes to the same block will overwrite the block buffer and the page buffer. a write to another block in the page will cause the addressed block to be loaded from the page buffer, and the write will be performed as described previously. the data width can be selected dynamically via t he datawidth input bus. the truth table for the data width settings is detailed in ta b l e 2 - 2 1 . the minimum resolvable address is one 8-bit byte. for data widths greater than 8 bits, the corresponding addr ess bits are ignored?when datawidth = 0 (2 bytes), addr[0] is ignored, and when datawidt h = '10' or '11' (4 bytes), addr [1:0] are ignored. data pins are lsb-oriented and unused wd data pins must be grounded. flash memory block protection page loss protection when the pagelossprotect pin is set to logic 1, it prevents writ es to any page other than the current page in the page buffer until the page is either discarded or programmed. a write to another page while the current page is page loss protected will return a status of '11'. overwrite protection any page that is overwrite protected will result in the status being set to '01' when an attempt is made to either write, program, or erase it. to set the overwrite protection state for a page, set the overwriteprotect pin when a program operation is undertaken. to clear the overwrite protect state for a given page, an unprotect page operatio n must be performed on the page, and then the page must be programmed with the overwriteprotect pin cleared to save the new page. lockrequest the lockrequest signal is used to give the user interface control over simultaneous access of the fb from both the user and jtag inte rfaces. when lockrequest is asse rted, the jtag interface will hold off any access attempts unt il lockrequest is deasserted. flash memory block operations fb operation priority the fb provides for priority of operations when multiple actions are requested simultaneously. table 2-22 shows the priority order (p riority 0 is the highest). table 2-21 ? data width settings datawidth[1:0] data width 00 1 byte [7:0] 01 2 byte [15:0] 10, 11 4 bytes [31:0] table 2-22 ? fb operation priority operation priority system initialization 0 fb reset 1 read 2 write 3 erase page 4 program 5 unprotect page 6 discard page 7
fusion family of mixed signal fpgas revision 4 2-47 access to the fb is controlled by the busy signal. the busy output is synchronous to the clk signal. fb operations are only accepted in cycles where busy is logic 0. write operation write operations are initiated with the assertion of the wen signal. figure 2-35 on page 2-47 illustrates the multiple write operations. when a write operation is initiated to a page that is currently not in t he page buffer, the fb control logic will issue a busy signal to the user interface while the page is loaded from the fb array into the page buffer. a copy page ope ration takes no less than 55 cycles and co uld take more if a write or unprotect page operation is started while the nvm is busy pre-fe tching a block. the basic operation is to read a block from the array into the block register (5 cycles ) and then write the block register to the page buffer (1 cycle) and if necessary, when the copy is comp lete, reading the block being written from the page buffer into the block buffer (1 cycle). a page contai ns 9 blocks, so 9 blocks multiplied by 6 cycles to read/write each block, plus 1 is 55 cycles total. subs equent writes to the same bl ock of the page will incur no busy cycles. a write to another block in the page will assert busy for four cycles (five cycles when pipe is asserted), to allow the data to be written to the page buffer and have the current block loaded into the block buffer. write operations are considered successful as long as the status output is '00'. a non-zero status indicates that an error was detected during the operation and the write was not performed. note that the status output is "sticky"; it is uncha nged until another o peration is started. only one word can be written at a time. write word width is controlled by the datawidth bus. users are responsible for keeping track of the contents of the page buffer and when to program it to the array. just like a regular ram, writing to random addresses is po ssible. users can write into the page buffer in any order but will incur additional busy cycles. it is not necessary to modi fy the entire page buffer before saving it to nonvolatile memory. write errors include the following: 1. attempting to write a page that is overwr ite protected (status = '0 1'). the write is not performed. 2. attempting to write to a page that is not in the page buffer when page loss protection is enabled (status = '11'). the wr ite is not performed. figure 2-35 ? fb write waveform clk wen addr[17:0] wd[31:0] datawidth[1:0] pagelossprotect busy status[1:0] a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 s0 s1 s2 s3 s4 s5 s6
device architecture 2-48 revision 4 program operation a program operation is initiated by asserting th e program signal on the interface. program operations save the contents of the page buffer to the fb array. due to the technologies inherent in the fb, a program operation is a time consum ing operation (~8 ms). while the fb is writing the data to the array, the busy signal will be asserted. during a program operation, the sector and page addresses on addr are compared with the stored address for the page (and sector) in the page buffer. if there is a mismatch between the two addresses, the program operation will be aborted and an e rror will be reported on the status output. it is possible to write the page buffer to a differ ent page in memory. when asserting the program pin, if overwritepage is asserted as well, the fb will write the contents of the page buffer to the sector and page designated on the addr inputs if the destination page is not overwrite protected. a program operation can be utilized to either modify the contents of the page in the flash memory block or change the protections for the page. setting th e overwriteprotect bit on the interface while asserting the program pin will put the page addresse d into overwrite protect mode. overwrite protect mode safeguards a page from being inadvertently overwritten during subsequent program or erase operations. program operations that result in a status value of '01' do not modi fy the addressed page. for all other values of status, the addressed page is modified. program errors include the following: 1. attempting to program a page that is overwrite protecte d (status = '01') 2. attempting to program a page that is not in t he page buffer when the page buffer has entered page loss protection mode (status = '01') 3. attempting to perform a program with over writepage set when the page addressed has been overwrite protected (status = '01') 4. the write count of the page programmed exceeding the write threshold defined in the part specification (status = '11') 5. the ecc logic determining that there is an uncorrectable error within the programmed page (status = '10') 6. attempting to program a page that is not in the page buffer when overwritepage is not set and the page in the page buffer is modified (status = '01') 7. attempting to program the page in the page buffer when the page buffer is not modified the waveform for a program operation is shown in figure 2-36 . note: overwritepage is only sampl ed when the program or erasepage pins are asserted. overwritepage is ignored in all other operations. figure 2-36 ? fb program waveform clk program addr[17:0] overwritepage overwriteprotect pagelossprotect busy status[1:0] page 0 valid
fusion family of mixed signal fpgas revision 4 2-49 erase page operation the erase page operation is initiated when the er asepage pin is asserted. the erase page operation allows the user to erase (set user data to zero) any page within the fb. the use of the overwritepage and pagelossprotect pins is t he same for erase as for a program page operation. as with the program page operation, a status of '01' indicates that the addressed page is not erased. a waveform for an erase page operation is shown in figure 2-37 . erase errors include the following: 1. attempting to erase a page that is overwrite protecte d (status = '01') 2. attempting to erase a page that is not in the page buffer when the page buffer has entered page loss protection mode (status = '01') 3. the write count of the erased page exceedi ng the write threshold defined in the part specification (status = '11') 4. the ecc logic determining that there is an uncorrectable error within the erased page (status = '10') figure 2-37 ? fb erase page waveform clk erase addr[17:0] overwriteprotect pagelossprotect busy status[1:0] page valid
device architecture 2-50 revision 4 read operation read operations are designed to read data from t he fb array, page buffer, block buffer, or status registers. read operations s upport a normal read and a read-ahead mode (done by asserting readnext). also, the timing for read oper ations is dependent on the setting of pipe. the following diagrams illustrate representative timing for non-pipe mode ( figure 2-38 ) and pipe mode ( figure 2-39 ) reads of the flash memo ry block interface. figure 2-38 ? read waveform (non-pipe mode, 32-bit access) figure 2-39 ? read waveform (pipe mode, 32-bit access) clk ren addr[17:0] datawidth[1:0] busy status[1:0] rd[31:0] a0 a1 a2 a3 a4 0 s0s1s2 s4 0d0d1d20 d3 0 s3 d4 0 a0 a1 a2 a3 a4 0s0s1s2 d2 s4 0 0 d0 d1 d4 x0 clk ren addr[17:0] datawidth[1:0] busy status[1:0] rd[31:0] s3 0 d3
fusion family of mixed signal fpgas revision 4 2-51 the following error indications are possible for read operations: 1. status = '01' when a single-bit data error was detected and corrected within the block addressed. 2. status = '10' when a double-bit error was detected in the block addressed (note that the error is uncorrected). in addition to data reads, users can read the status of any page in the fb by asserting pagestatus along with ren. the format of the data returned by a page status read is shown in ta b l e 2 - 2 3 , and the definition of the page status bits is shown in ta b l e 2 - 2 4 . table 2-23 ? page status read data format 31 8 7 4 3 2 1 0 write count reserved over threshold read prot ected write protected overwrite protected table 2-24 ? page status bit definition page status bit(s) definition 31?8 the number of times the page addressed has been programmed/erased 7?4 reserved; read as 0 3 over threshold indicator (see the "program operation" section on page 2-48 ) 2 read protected; read protect bit for page , which is set via the jtag interface and only affects jtag operations. this bit can be overridden by using the correct user key value. 1 write protected; write protect bit for pa ge, which is set via the jtag interface and only affects jtag operations. this bit can be overridden by using the correct user key value. 0 overwrite protected; designates that the user has set the overwriteprotect bit on the interface while doing a program operation. the page cannot be written without first performing an unprotect page operation.
device architecture 2-52 revision 4 read next operation the read next operation is a feature by which the next block relative to the block in the block buffer is read from the fb array while performing reads from t he block buffer. the goal is to minimize wait states during consecutive sequential read operations. the read next operation is performed in a predet ermined manner because it does look-ahead reads. the general look-ahead function is as follows: ? within a page, the next block fetched will be the next in linear address. ? when reading the last data block of a page, it will fetch the first block of the next page. ? when reading spare pages, it will read the fi rst block of the next sector's spare page. ? reads of the last sector will wrap around to sector 0. ? reads of auxiliary blocks will read the next linear page' s auxiliary block. when an address on the addr input does not agree with the predetermined look -ahead address, there is a time penalty for this access. the fb will be busy finishing the current look-ahead read before it can start the next read. the worst case is a total of nine busy cycles befor e data is delivered. the non-pipe mode and pipe mode waveforms for read next operations are illustrated in figure 2-40 and figure 2-41 . figure 2-40 ? read next waveform (non-pipe mode, 32-bit access) figure 2-41 ? read next waveform (pipe mode, 32-bit access) clk ren readnext addr[17:0] datawidth[1:0] busy status[1:0] rd[31:0] a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 0 s0s1s2 s4s5s6 s8s9 0d0d1d2 s3 d3 0 0 s7 d7 0 0 d4 d5 d6 d8 d9 clk ren readnext addr[17:0] busy status[1:0] rd[31:0] a0 a1 a2 a3 a4 a5 a6 a7 a8 s0 s1 s2 s4 s5 s6 0d0d1d2 s3 d3 0 0d4d5d6 s7 0 0 d7
fusion family of mixed signal fpgas revision 4 2-53 unprotect page operation an unprotect page operation will clear the protecti on for a page addressed on the addr input. it is initiated by setting the unprotectpage signal on the interface along with the page address on addr. if the page is not in the page buffer, the unprot ect page operation will copy the page into the page buffer. the copy page operation occurs only if t he current page in the page buffer is not page loss protected. the waveform for an unprotect page operation is shown in figure 2-42 . the unprotect page operation can incur the following error conditions: 1. if the copy of the page to the page buffer determines that the page has a single-bit correctable error in the data, it will report a status = '01'. 2. if the address on addr does not match the add ress of the page buffer, pagelossprotect is asserted, and the page buffer has been modified , then status = '11' and the addressed page is not loaded into the page buffer. 3. if the copy of the page to the page buffer determines that at least one block in the page has a double-bit uncorrectable error, status = '10' and the page buffer will contain the corrupted data. discard page operation if the contents of the modified page buffer have to be discarded, the discardpage signal should be asserted. this command results in the page buffer being marked as unmodified. the timing for the operation is shown in figure 2-43 . the busy signal will remain asserted until the operation has completed. figure 2-42 ? fb unprotected page waveform clk unprotectpage addr[17:0] busy status[1:0] page valid figure 2-43 ? fb discard page waveform clk discardpage busy
device architecture 2-54 revision 4 flash memory block characteristics figure 2-44 ? reset timing diagram table 2-25 ? flash memory block timing commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t clk2rd clock-to-q in 5-cycle read mode of the read data 7.99 9.10 10.70 ns clock-to-q in 6-cycle read mode of the read data 5.03 5.73 6.74 ns t clk2busy clock-to-q in 5-cycle read mode of busy 4.95 5.63 6.62 ns clock-to-q in 6-cycle read mode of busy 4.45 5.07 5.96 ns t clk2status clock-to-status in 5-cycle read mode 11.24 12.81 15.06 ns clock-to-status in 6-cycle read mode 4.48 5.10 6.00 ns t dsunvm data input setup time for the control logic 1.92 2.19 2.57 ns t dhnvm data input hold time for the control logic 0.00 0.00 0.00 ns t asunvm address input setup time for the control logic 2.76 3.14 3.69 ns t ahnvm address input hold time for the control logic 0.00 0.00 0.00 ns t sudwnvm data width setup time for the control logic 1.85 2.11 2.48 ns t hddwnvm data width hold time for the control logic 0.00 0.00 0.00 ns t surennvm read enable setup time for the control logic 3.85 4.39 5.16 ns t hdrennvm read enable hold time for the control logic 0.00 0.00 0.00 ns t suwennvm write enable setup time for the control logic 2.37 2.69 3.17 ns t hdwennvm write enable hold time for the control logic 0.00 0.00 0.00 ns t suprognvm program setup time for the c ontrol logic 2.16 2.46 2.89 ns t hdprognvm program hold time for the control logic 0.00 0.00 0.00 ns t susparepage sparepage setup time for the control logic 3.74 4.26 5.01 ns t hdsparepage sparepage hold time for the control logic 0.00 0.00 0.00 ns t suauxblk auxiliary block setup time for the control logic 3.74 4.26 5.00 ns t hdauxblk auxiliary block hold time for the control logic 0.00 0.00 0.00 ns t surdnext readnext setup time for the control logic 2.17 2.47 2.90 ns t hdrdnext readnext hold time for the control logic 0.00 0.00 0.00 ns t suerasepg erase page setup time for the control logic 3.76 4.28 5.03 ns t hderasepg erase page hold time for the control logic 0.00 0.00 0.00 ns t suunprotectpg unprotect page setup time for the control logic 2.01 2.29 2.69 ns t hdunprotectpg unprotect page hold time for the control logic 0.00 0.00 0.00 ns t sudiscardpg discard page setup time for the control logic 1.88 2.14 2.52 ns t hddiscardpg discard page hold time for the control logic 0.00 0.00 0.00 ns t suoverwrpro overwrite protect setup time for the control logic 1.64 1.86 2.19 ns t hdoverwrpro overwrite protect hold time for the control logic 0.00 0.00 0.00 ns clk reset active low, asynchronous busy
fusion family of mixed signal fpgas revision 4 2-55 t supglosspro page loss protect setup time for the control logic 1.69 1.93 2.27 ns t hdpglosspro page loss protect hold time for the control logic 0.00 0.00 0.00 ns t supgstat page status setup time for the control logic 2.49 2.83 3.33 ns t hdpgstat page status hold time for the control logic 0.00 0.00 0.00 ns t suoverwrpg over write page setup time for the control logic 1.88 2.14 2.52 ns t hdoverwrpg over write page hold time for the control logic 0.00 0.00 0.00 ns t sulockrequest lock request setup time for the control logic 0.87 0.99 1.16 ns t hdlockrequest lock request hold time for the control logic 0.00 0.00 0.00 ns t recarnvm reset recovery time 0.94 1.07 1.25 ns t remarnvm reset removal time 0.00 0.00 0.00 ns t mpwarnvm asynchronous reset minimum pulse width for the control logic 10.00 12.50 12.50 ns t mpwclknvm clock minimum pulse width for the control logic 4.00 5.00 5.00 ns t fmaxclknvm maximum frequency for clock for the control logic ? for afs1500/afs600 80.00 80.00 80.00 mhz maximum frequency for clock for the control logic ? for afs250/afs090 100.00 80.00 80.00 mhz table 2-25 ? flash memory block timing (continued) commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units
device architecture 2-56 revision 4 flashrom fusion devices have 1 kbit of on-chip nonvolatile fl ash memory that can be read from the fpga core fabric. the flashrom is arranged in eight banks of 128 bits during programming. the 128 bits in each bank are addressable as 16 bytes during the read- back of the flashrom from the fpga core ( figure 2- 45 ). the flashrom can only be programmed via the ieee 1532 jtag port. it cannot be programmed directly from the fpga core. when programming, each of the eight 128-bit banks can be selectively reprogrammed. the flashrom can only be reprogr ammed on a bank boundary. programming involves an automatic, on-chip bank erase prior to reprogramming the bank. the flashrom supports a synchronous read and can be read on byte boundaries. the upper three bits of the flashrom address from the fpga core define the bank that is bei ng accessed. the lower four bits of the flashrom address from the fpga core define which of the 16 bytes in the bank is being accessed. the maximum flashrom access clock is given in table 2-26 on page 2-57 . figure 2-46 shows the timing behavior of the flashrom access cycle?the address has to be set up on the rising edge of the clock for dout to be valid on the next falling edge of the clock. if the address is unchanged for two cycles: ? d0 becomes invalid t ck2q ns after the second rising edge of the clock. ? d0 becomes valid again t ck2q ns after the second falling edge. if the address unchanged for three cycles: ? d0 becomes invalid t ck2q ns after the second rising edge of the clock. ? d0 becomes valid again t ck2q ns after the second falling edge. ? d0 becomes invalid t ck2q ns after the third rising edge of the clock. ? d0 becomes valid again t ck2q ns after the third falling edge. figure 2-45 ? flashrom architecture bank number 3 msb of addr (read) byte number in bank 4 lsb of addr (read) 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
fusion family of mixed signal fpgas revision 4 2-57 flashrom characteristics figure 2-46 ? flashrom timing diagram table 2-26 ? flashrom access time commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t su address setup time 0.53 0.61 0.71 ns t hold address hold time 0.00 0.00 0.00 ns t ck2q clock to out 21.42 24.40 28.68 ns f max maximum clock frequency 15.00 15.00 15.00 mhz t su t hold address a0 t ck2q d0 d0 a1 t su t hold t ck2q d1 t su t hold t ck2q
device architecture 2-58 revision 4 sram and fifo all fusion devices have sram blocks along the north side of the device. additionally, afs600 and afs1500 devices have an sram block on the sout h side of the device. to meet the needs of high- performance designs, the memory bl ocks operate strictly in synchronous mode fo r both read and write operations. the read and write clocks are completely independent, and each may operate at any desired frequency less than or equal to 350 mhz. the following configurations are available: ? 4k1, 2k2, 1k4, 5129 (dual-port ram?two read, two write or one read, one write) ? 5129, 25618 (two-port ram?one read and one write) ? sync write, sync pipelined/nonpipelined read the fusion sram memory block includes dedicated fi fo control logic to generate internal addresses and external flag logic (ful l, empty, afull, aempty). during ram operation, addresses are sourced by the us er logic, and the fifo controller is ignored. in fifo mode, the internal addresses are generated by the fifo controller and routed to the ram array by internal muxes. refer to figure 2-47 for more information about the implementation of the embedded fifo controller. the fusion architecture enables the read and wr ite sizes of rams to be organized independently, allowing for bus conversion. this is done with the ww (write width) and rw (read width) pins. the different dw configurations are 25618, 5129, 1k4, 2k2, and 4k1. for example, the write size can be set to 25618 and the read size to 5129. both the write and read widths for the ram blocks can be specified independently with the ww (write width) and rw (read width) pins. the different dw configurations are 25618, 5129, 1k4, 2k2, and 4k1. refer to the allowable rw and ww values s upported for each of the ram macro types in table 2-27 on page 2-61 . when a width of one, two, or four is selected, the ninth bit is unus ed. for example, when writing 9-bit values and reading 4-bit values, only the first four bi ts and the second four bits of each 9-bit value are addressable for read operations. the ninth bit is not accessible.
fusion family of mixed signal fpgas revision 4 2-59 conversely, when writing 4-bit values and reading 9- bit values, the ninth bit of a read operation will be undefined. the ram blocks employ little-endian byte order fo r read and wr ite operations. figure 2-47 ? fusion ram block with embedded fifo controller rclk wd wclk reset rblk ren estop wblk wen fstop rd[17:0] wd[17:0] rclk wclk radd[j:0] wadd[j:0] ren fren fwen wen full aempty afull empty rd rpipe rw[2:0] ww[2:0] ram cnt 12 e = e = afval aeval sub 12 cnt 12
device architecture 2-60 revision 4 ram4k9 description figure 2-48 ? ram4k9 addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 reset
fusion family of mixed signal fpgas revision 4 2-61 the following signals are used to c onfigure the ram4k9 memory element: widtha and widthb these signals enable the ram to be configured in one of four allowable aspect ratios ( table 2-27 ). blka and blkb these signals are active low and will enable the respective ports when asserted. when a blkx signal is deasserted, the corresponding port?s outputs hold the previous value. wena and wenb these signals switch the ram between read and writ e mode for the respective ports. a low on these signals indicates a write operation, and a high indicates a read. clka and clkb these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. pipea and pipeb these signals are used to specify pipelined read on th e output. a low on pipea or pipeb indicates a nonpipelined read, and the data appears on the corresp onding output in the same clock cycle. a high indicates a pipelined, read and data appears on the corresponding output in the next clock cycle. wmodea and wmodeb these signals are used to configure the behavior of th e output when the ram is in write mode. a low on these signals makes the output retain data from the previous read. a high indicates pass-through behavior, wherein the data being written will appear i mmediately on the output. this signal is overridden when the ram is being read. reset this active low signal resets the output to zero, disables reads and writes from the sram block, and clears the data hold registers when asserted. it does not reset the contents of the memory. addra and addrb these are used as read or write addresses, and they are 12 bits wide. when a depth of less than 4 k is specified, the unus ed high-order bits must be grounded ( table 2-28 ). table 2-27 ? allowable aspect ratio settings for widtha[1:0] widtha1, widtha0 wi dthb1, widthb0 dw 00 00 4k1 01 01 2k2 10 10 1k4 11 11 5129 note: the aspect ratio settings are constant and cannot be changed on the fly. table 2-28 ? address pins unused/used for various supported bus widths dw addrx unused used 4k1 none [11:0] 2k2 [11] [10:0] 1k4 [11:10] [9:0] 5129 [11:9] [8:0] note: the "x" in addrx implies a or b.
device architecture 2-62 revision 4 dina and dinb these are the input data signals, and they are nine bits wide. not all nine bits are valid in all configurations. when a data width less than nine is specified, unused high-order signals must be grounded ( ta b l e 2 - 2 9 ). douta and doutb these are the nine-bit output data si gnals. not all nine bits are valid in all configurations. as with dina and dinb, high-order bits may not be used ( ta b l e 2 - 2 9 ). the output data on unused pins is undefined. table 2-29 ? unused/used input and output data pins for various supported bus widths dw dinx/doutx unused used 4k1 [8:1] [0] 2k2 [8:2] [1:0] 1k4 [8:4] [3:0] 5129 none [8:0] note: the "x" in dinx and doutx implies a or b.
fusion family of mixed signal fpgas revision 4 2-63 ram512x18 description figure 2-49 ? ram512x18 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset
device architecture 2-64 revision 4 ram512x18 exhibits slightly differ ent behavior from ram4k9, as it has dedicated read and write ports. ww and rw these signals enable the ram to be configured in one of the two allowable aspect ratios ( table 2-30 ). wd and rd these are the input and output data signals, and they are 18 bits wide. when a 5129 aspect ratio is used for write, wd[17:9] are unused and must be gro unded. if this aspect rati o is used for read, then rd[17:9] are undefined. waddr and raddr these are read and write addresses, and they are nine bits wide. when the 25618 aspect ratio is used for write or read, waddr[8] or radd r[8] are unused and must be grounded. wclk and rclk these signals are the write and read clocks, respectively. they are both active high. wen and ren these signals are the write and read enables, respecti vely. they are both active low by default. these signals can be configured as active high. reset this active low signal resets the output to zero, di sables reads and/or writes from the sram block, and clears the data hold registers when asserted. it does not reset the contents of the memory. pipe this signal is used to specify pipelined read on the output. a low on pipe indicates a nonpipelined read, and the data appears on the output in the same clock cycle. a high indicates a pipelined read, and data appears on the output in the next clock cycle. clocking the dual-port sram blocks are only clocked on the rising edge. sm artgen allows falli ng-edge-triggered clocks by adding inverters to the netlist, hence ac hieving dual-port sram blocks that are clocked on either edge (rising or falling). for dual-port sram , each port can be clocked on either edge or by separate clocks, by port. fusion devices support inversion (bubble pushing) thro ughout the fpga architectu re, including the clock input to the sram modules. inversions added to the sram clock pin on the design schematic or in the hdl code will be automatically accounted for during de sign compile without incurring additional delay in the clock path. the two-port sram can be clocked on the ri sing edge or falling edge of wclk and rclk. if negative-edge ram and fifo clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automatically used within the fusion development tools, without performance penalty. table 2-30 ? aspect ratio sett ings for ww[1:0] ww[1:0] rw[1:0] dw 01 01 5129 10 10 25618 00, 11 00, 11 reserved
fusion family of mixed signal fpgas revision 4 2-65 modes of operation there are two read mode s and one write mode: ? read nonpipelined (synchronous?1 clock edge): in the standard read mode, new data is driven onto the rd bus in the same clock cycle follo wing ra and ren valid. the read address is registered on the read port clock active edge, and data appears at rd after the ram access time. setting pipe to off enables this mode. ? read pipelined (synchronous?2 clock edges): the pipelined mode incurs an additional clock delay from the address to the da ta but enables operation at a much higher frequency. the read address is registered on the read port active clock edge, and the read data is registered and appears at rd after the second read clock edge. setting pipe to on enables this mode. ? write (synchronous?1 clock edge) : on the write clock active edge, the write data is written into the sram at the write address when wen is hi gh. the setup times of the write address, write enables, and write data are minimal with respect to the write clock. writ e and read transfers are described with timing requirements in the "sram characteristics" section on page 2-66 and the "fifo characteristics" section on page 2-75 . ram initialization each sram block can be individually initialized on power-up by means of the jtag port using the ujtag mechanism (refer to the "jtag ieee 1532" section on page 2-232 and the fusion sram/fifo blocks application note). the shift register for a target block can be selected and loaded with the proper bit configuration to enable serial loading. the 4,608 bits of data can be loaded in a single operation.
device architecture 2-66 revision 4 sram characteristics timing waveforms figure 2-50 ? ram read for flow-through output. applicable to both ram4k9 and ram512x18. figure 2-51 ? ram read for pipelined output. appl icable to both ram4k9 and ram512x18. clk [r|w]addr blk wen dout|rd a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk [r|w]addr blk wen dout|rd a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
fusion family of mixed signal fpgas revision 4 2-67 figure 2-52 ? ram write, output retained. applicable to both ram4k9 and ram512x18. figure 2-53 ? ram write, output as write data (wmode = 1). applicable to ram4k9 only. t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk wen [r|w]addr din|wd d n dout|rd t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 t as t ah t bks t ens t ds t dh clk blk wen addr din t bkh dout (flow-through) dout (pipelined) di 0 di 1 d n di 0 di 1 d n di 1 di 2 d 0
device architecture 2-68 revision 4 figure 2-54 ? one port write / other port read same figure 2-55 ? ram reset. applicable to both ram4k9 and ram512x18. a 0 a 2 a 3 a 0 a 1 a 4 clk1 addr1 clk2 addr2 din1 d 0 d 2 d 3 d 0 d 1 d 0 dout2 (flow-through) dout2 (pipelined) t ckq2 t ckq1 t wro t as t ah t ds t dh t as t ah d n d n clk reset dout|rd d n t cyc t ckh t ckl t rstbq d m
fusion family of mixed signal fpgas revision 4 2-69 timing characteristics table 2-31 ? ram4k9 commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren, wen setup time 0.14 0.16 0.19 ns t enh ren, wen hold time 0.10 0.11 0.13 ns t bks blk setup time 0.23 0.27 0.31 ns t bkh bl hold time 0.02 0.02 0.02 ns t ds input data (din) setup time 0.18 0.21 0.25 ns t dh input data (din) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on dout (out put retained, wmode = 0) 1.79 2.03 2.39 ns clock high to new data valid on dout (flo w-through, wmode = 1) 2.36 2.68 3.15 ns t ckq2 clock high to new data valid on dout (pipelined) 0.89 1.02 1.20 ns t c2cwwh 1 address collision clk-to-clk delay for reliable write after write on same address?applicable to rising edge 0.30 0.26 0.23 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address?applicable to opening edge 0.45 0.38 0.34 ns t c2cwrh 1 address collision clk-to-clk delay for reliable write access after read on same address? applicable to opening edge 0.49 0.42 0.37 ns t rstbq reset low to data out low on dout (flow-through) 0.92 1.05 1.23 ns reset low to data out low on dout (pipelined) 0.92 1.05 1.23 ns t remrstb reset removal 0.29 0.33 0.38 ns t recrstb reset recovery 1.50 1.71 2.01 ns t mpwrstb reset minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-70 revision 4 table 2-32 ? ram512x18 commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren, wen setup time 0.09 0.10 0.12 ns t enh ren, wen hold time 0.06 0.07 0.08 ns t ds input data (wd) setup time 0.18 0.21 0.25 ns t dh input data (wd) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on rd (output retained) 2.16 2.46 2.89 ns t ckq2 clock high to new data valid on rd (pipelined) 0.90 1.02 1.20 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address?applicabl e to opening edge 0.50 0.43 0.38 ns t c2cwrh 1 address collision clk-to-c lk delay for reliable write access after read on same address? applicable to opening edge 0.59 0.50 0.44 ns t rstbq 1 reset low to data out low on rd (flow-through) 0.92 1.05 1.23 ns reset low to data out low on rd (pipelined) 0.92 1.05 1.23 ns t remrstb reset removal 0.29 0.33 0.38 ns t recrstb reset recovery 1.50 1.71 2.01 ns t mpwrstb reset minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-71 fifo4k18 description figure 2-56 ? fifo4kx18 fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
device architecture 2-72 revision 4 the following signals are used to c onfigure the fifo4k18 memory element: ww and rw these signals enable the fifo to be configured in one of the five allowable aspect ratios ( ta b l e 2 - 3 3 ). wblk and rblk these signals are active low and will enable the respective ports when low. when the rblk signal is high, the corresponding port?s outputs hold the previous value. wen and ren read and write enables. wen is active low and ren is active high by default. these signals can be configured as active high or low. wclk and rclk these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. rpipe this signal is used to specify pipelined read on the output. a low on rpipe indicates a nonpipelined read, and the data ap pears on the outp ut in the same clock cycle. a hig h indicates a pipel ined read, and data appears on the output in the next clock cycle. reset this active low signal resets the output to zero when asserted. it resets the fifo counters. it also sets all the rd pins low, the full and afull pins low, and the empty and aempty pins high ( ta b l e 2 - 3 4 ). wd this is the input data bus and is 18 bits wide. not a ll 18 bits are valid in all configurations. when a data width less than 18 is specified, unused higher-order signals must be grounded ( table 2-34 ). rd this is the output data bus and is 18 bits wide. not all 18 bits are valid in all configurations. like the wd bus, high-order bits become unusable if the data width is less than 18. the output data on unused pins is undefined ( ta b l e 2 - 3 4 ). estop, fstop estop is used to stop the fifo read counter from further counting once the fifo is empty (i.e., the empty flag goes high). a high on this signal inhibits the counting. table 2-33 ? aspect ratio sett ings for ww[2:0] ww2, ww1, ww0 rw2, rw1, rw0 d w 000 000 4k1 001 001 2k2 010 010 1k4 011 011 5129 100 100 25618 101, 110, 111 101, 110, 111 reserved table 2-34 ? input data signal usage for different aspect ratios dw wd/rd unused 4k 1 wd[17:1], rd[17:1] 2k 2 wd[17:2], rd[17:2] 1k 4 wd[17:4], rd[17:4] 512 9 wd[17:9], rd[17:9] 256 18 ?
fusion family of mixed signal fpgas revision 4 2-73 fstop is used to stop the fifo write counter from fu rther counting once the fifo is full (i.e., the full flag goes high). a high on this signal inhibits the counting. for more information on these signals, refer to the "estop and fstop usage" section on page 2-73 . full, empty when the fifo is full and no more data can be writt en, the full flag asserts high. the full flag is synchronous to wclk to inhibit writing immediat ely upon detection of a full condition and to prevent overflows. since the write address is compared to a resynchronized (and thus time-delayed) version of the read address, the full flag will remain asserted until two wclk active edges after a read operation eliminates the full condition. when the fifo is empty and no more data can be read, the empty flag asserts high. the empty flag is synchronous to rclk to inhibit reading immedi ately upon detection of an empty condition and to prevent underflows. since the read address is comp ared to a resynchronized (and thus time-delayed) version of the write address, the empty flag will re main asserted until two rclk active edges after a write operation removes the empty condition. for more information on th ese signals, refer to the "fifo flag usage considerations" section on page 2-74 . afull, aempty these are programmable flags and will be asserted on the threshold specified by afval and aeval, respectively. when the number of words stored in the fifo reac hes the amount specified by aeval while reading, the aempty output will go high. likewise, when the numb er of words stored in the fifo reaches the amount specified by afval while writi ng, the afull out put will go high. afval, aeval the aeval and afval pins are used to specify the almost-empty and almost-full threshold values, respectively. they are 12-bit signals. for more information on these signals, refer to "fifo flag usage considerations" section . estop and fstop usage the estop pin is used to stop the read counter from counting any furt her once the fifo is empty (i.e., the empty flag goes high). likewise, the fstop pin is used to stop the writ e counter from counting any further once the fifo is full (i.e., the full flag goes high). the fifo counters in the fusion device start the count at 0, reach the maximum depth for the configuration (e.g., 511 for a 5129 configuration), a nd then restart at 0. an example application for the estop, where the read counter keeps counting, woul d be writing to the fifo once and reading the same content over and over wi thout doing another write.
device architecture 2-74 revision 4 fifo flag usage considerations the aeval and afval pins are used to specif y the 12-bit aempty and afull threshold values, respectively. the fifo contains separate 12-bit write address (waddr) and read address (raddr) counters. waddr is incremented every time a writ e operation is performed, and raddr is incremented every time a read operation is performed. w henever the difference between waddr and raddr is greater than or equal to afval, the afull output is asserted. likewise, whenever the difference between waddr and raddr is less than or equal to aeval, the aempty output is asserted. to handle different read and write aspect ratios, afval and aeval are expressed in terms of total data bits instead of total data words. when users specify afval and aeval in terms of read or write words, the smartgen tool translates them into bit addresses a nd configures these signal s automatically. smartgen configures the afull flag to assert when the writ e address exceeds the read address by at least a predefined value. in a 2k8 fifo, for example, a value of 1,500 for afval means that the afull flag will be asserted after a write when the difference between the write address and the read address reaches 1,500 (there have been at least 1500 more writes than reads). it will stay asserted until the difference between the write and read addresses drops below 1,500. the aempty flag is asserted when the difference between the write address and the read address is less than a predefined value. in the example above, a value of 200 for aeval means that the aempty flag will be asserted when a read causes the differ ence between the write addr ess and the read address to drop to 200. it will stay asserted until that difference rises above 200. note that the fifo can be configured with different read and write widths; in this case, the afval setting is based on the number of write data entries and the aeval setting is based on the number of read data entries. for aspect ratios of 5129 and 25618, only 4,096 bits can be addressed by the 12 bits of afval and aeval. the number of words must be multiplied by 8 and 16, instead of 9 and 18. the smartgen tool automatically uses the proper values. to avoid halfwords being written or read, which could happen if different read and write aspect ratios are specified, the fi fo will assert full or empty as soon as at least a minimum of one word cannot be written or read. for example, if a two- bit word is written and a four-bit word is being read, the fifo will remain in the empty stat e when the first word is written. this occurs even if the fifo is not completely empty, because in this case, a complete word cannot be read. the same is applicable in the full state. if a four-bit word is written and a two-bit wo rd is read, the fifo is full and one word is read. the full flag will remain asserted because a comple te word cannot be written at this point.
fusion family of mixed signal fpgas revision 4 2-75 fifo characteristics timing waveforms figure 2-57 ? fifo read figure 2-58 ? fifo write t ens t enh t ckq1 t ckq2 t cyc d 0 d 1 d n d n d 0 d 2 d 1 t bks t bkh rclk rblk ren rd (flow-through) rd (pipelined) wclk wen wd t ens t enh t ds t dh t cyc di 0 di 1 t bkh t bks wblk
device architecture 2-76 revision 4 figure 2-59 ? fifo reset figure 2-60 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset ef aef wa/ra (address counter) t rstfg t rstaf ff aff rclk no match no match dist = aef_th match (empty) t ckaf t rckef ef aef t cyc wa/ra (address counter)
fusion family of mixed signal fpgas revision 4 2-77 figure 2-61 ? fifo full and afull flag assertion figure 2-62 ? fifo empty flag and aempty flag deassertion figure 2-63 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk ff aff wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk ef 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aef rclk wa/ra (address counter) match (full) no match no match no match dist = aff_th ? 1 no match wclk ff 1st rising edge after 1st read 1st rising edge after 2nd read t wckf t ckaf aff
device architecture 2-78 revision 4 timing characteristics table 2-35 ? fifo commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t ens ren, wen setup time 1.34 1.52 1.79 ns t enh ren, wen hold time 0.00 0.00 0.00 ns t bks blk setup time 0.19 0.22 0.26 ns t bkh blk hold time 0.00 0.00 0.00 ns t ds input data (wd) setup time 0.18 0.21 0.25 ns t dh input data (wd) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on rd (flow-through) 2.17 2.47 2.90 ns t ckq2 clock high to new data valid on rd (pipelined) 0.94 1.07 1.26 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 ns t ckaf clock high to almost empty/full flag valid 6.19 7.05 8.29 ns t rstfg reset low to empty/full flag valid 1.69 1.93 2.27 ns t rstaf reset low to almost-empty/full flag valid 6.13 6.98 8.20 ns t rstbq reset low to data out low on rd (flow-through) 0.92 1.05 1.23 ns reset low to data out low on rd (pipelined) 0.92 1.05 1.23 ns t remrstb reset removal 0.29 0.33 0.38 ns t recrstb reset recovery 1.50 1.71 2.01 ns t mpwrstb reset minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency for fifo 310 272 231 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-79 analog block with the fusion family, microsemi has introduced the world's first mixed-mode fpga solution. supporting a robust analog peripheral mix, fusion devic es will support a wide variety of applications. it is this analog block that separates fusion from all other fpga solutions on the market today. by combining both flash and high-speed cmos processes in a single chip, these devices offer the best of both worlds. the high-performance cmos is used for building ram resources. these high- performance structures support device operation up to 350 mhz. additionally, the advanced microsemi 0.13 m flash process incorporates high-voltage transi stors and a high-isolation, triple-well process. both of these are suited for the flash-based programm able logic and nonvolatile memory structures. high-voltage transistors support the integration of analog technology in several ways. they aid in noise immunity so that the analog portions of the chip can be better isolated from the digital portions, increasing analog accuracy. because they support high voltages, microsemi flash fpgas can be connected directly to high-voltage input signals, eliminating the need for external resistor divider networks, reducing component count, and increasing accuracy. by supporting higher internal voltages, the microsemi advanced flash process enables high dynamic range on analog circuitry, increasing precision and signal?noise ratio. microsemi flash fp gas also drive high-voltage outputs, eliminating the need for external level shifters and drivers. the unique triple-well process enables the integr ation of high-performance analog features with increased noise immunity and better isolation. by increasing the efficiency of analog design, the triple- well process also enables a smaller overall design size, reducing die size and cost. the analog block consists of the analog quad i/o structure, rtc (for details refer to the "real-time counter system" section on page 2-33 ), adc, and acm. all of thes e elements are combined in the single analog block macro, with which the user implements this functionality ( figure 2-64 ). the analog block needs to be reset/reinitialized after the core powers up or the device is programmed. an external reset/initialize signal, which can come from the internal voltage regulator when it powers up, must be applied.
device architecture 2-80 revision 4 figure 2-64 ? analog block macro varef adcgndref av0 ac0 at0 av9 ac9 at9 atreturn01 atreturn9 denav0 denac0 davout0 dacout0 datout0 dacout9 davout9 datout9 ag1 ag0 ag9 denat0 denav0 denac0 denat0 cmstb0 csmtb9 gdon0 gdon9 tmstb0 tmstb9 mode[3:0] tvc[7:0] stc[7:0] chnumber[4:0] tmstint adcstart varefsel pwrdwn adcreset busy calibrate datav alid sample result[11:0] rtcmatch rtcxtlmode rtcxtlsel rtcpsmmatch rtcclk sysclk acmwen acmrdata[7:0] acmreset acmwdata acmaddr acmclk ab
fusion family of mixed signal fpgas revision 4 2-81 table 2-36 describes each pin in the analog block. each function within the analog block will be explained in detail in the following sections. table 2-36 ? analog block pin description signal name number of bits direction function location of details varef 1 input/output voltage reference for adc adc adcgndref 1 input external ground reference adc mode[3:0] 4 input adc operating mode adc sysclk 1 input external system clock tvc[7:0] 8 input clock divide control adc stc[7:0] 8 input sample time control adc adcstart 1 input start of conversion adc pwrdwn 1 input adc comparator power-down if 1. when asserted, the adc will stop functioning, and the digital portion of the analog block will continue operating. this may result in invalid status flags from the analog block. therefore, microsemi does not recommend asserting the pwrdwn pin. adc adcreset 1 input adc resets and disables analog quad ? active high adc busy 1 output 1 ? running conversion adc calibrate 1 output 1 ? power-up calibration adc datavalid 1 output 1 ? valid conversion result adc result[11:0] 12 output conversion result adc tmstbint 1 input internal temp. monitor strobe adc sample 1 output 1 ? an analog signal is actively being sampled (stays high during signal acquisition only) 0 ? no analog signal is being sampled adc varefsel 1 input 0 = output internal voltage reference (2.56 v) to varef 1 = input external voltage reference from varef and adcgndref adc chnumber[4:0] 5 input analog input channel select input multiplexer acmclk 1 input acm clock acm acmwen 1 input acm write enable ? active high acm acmreset 1 input acm reset ? active low acm acmwdata[7:0] 8 input acm write data acm acmrdata[7:0] 8 output acm read data acm acmaddr[7:0] 8 input acm address acm cmstb0 to cmstb9 10 input current monitor strobe ? 1 per quad, active high analog quad
device architecture 2-82 revision 4 gdon0 to gdon9 10 input control to power mos ? 1 per quad analog quad tmstb0 to tmstb9 10 input temperature monitor strobe ? 1 per quad; active high analog quad davout0, dacout0, datout0 to davout9, dacout9, datout9 30 output digital outputs ? 3 per quad analog quad denav0, denac0, denat0 to denav9, denac9, denat9 30 input digital input enables ? 3 per quad analog quad av0 1 input analog quad 0 analog quad ac0 1 input analog quad ag0 1 output analog quad at0 1 input analog quad atreturn01 1 input temperature monitor return shared by analog quads 0 and 1 analog quad av1 1 input analog quad 1 analog quad ac1 1 input analog quad ag1 1 output analog quad at1 1 input analog quad av2 1 input analog quad 2 analog quad ac2 1 input analog quad ag2 1 output analog quad at2 1 input analog quad atreturn23 1 input temperature monitor return shared by analog quads 2 and 3 analog quad av3 1 input analog quad 3 analog quad ac3 1 input analog quad ag3 1 output analog quad at3 1 input analog quad av4 1 input analog quad 4 analog quad ac4 1 input analog quad ag4 1 output analog quad at4 1 input analog quad atreturn45 1 input temperature monitor return shared by analog quads 4 and 5 analog quad av5 1 input analog quad 5 analog quad ac5 1 input analog quad ag5 1 output analog quad at5 1 input analog quad av6 1 input analog quad 6 analog quad ac6 1 input analog quad table 2-36 ? analog block pin description (continued) signal name number of bits direction function location of details
fusion family of mixed signal fpgas revision 4 2-83 analog quad with the fusion family, microsemi in troduces the anal og quad, shown in figure 2-65 on page 2-84 , as the basic analog i/o structure. the analog quad is a four-channel system used to precondition a set of analog signals before sending it to the adc for conversion into a digital signal. to maximize the usefulness of the analog quad, th e analog input signals can also be configured as lvttl digital input signals. the analog quad is divided into four sections. the first section is called the voltage monitor block, and its input pin is named av. it contains a two- channel analog multiplexer that allows an incoming analog signal to be routed directly to the adc or allows the signal to be routed to a prescaler circuit before being sent to the adc. the prescaler can be configured to accept analog signals between ?12 v and 0 or between 0 and +12 v. the prescaler circuit scales the voltage applied to the adc input pad such that it is compatible wi th the adc input voltage range. the av pin can also be used as a digital input pin. the second section of the analog quad is called the current monitor block. its input pin is named ac. the current monitor block contains all the same functions as the voltage monitor block with one addition, which is a current monitori ng function. a small external current sensing resistor (typically less than 1 ? ) is connected between the av and ac pins and is in series with a power source. the current monitor block contains a current monitor circuit that converts the current through the external resistor to a voltage that can then be read using the adc. ag6 1 output analog quad at6 1 input analog quad atreturn67 1 input temperature monitor return shared by analog quads 6 and 7 analog quad av7 1 input analog quad 7 analog quad ac7 1 input analog quad ag7 1 output analog quad at7 1 input analog quad av8 1 input analog quad 8 analog quad ac8 1 input analog quad ag8 1 output analog quad at8 1 input analog quad atreturn89 1 input temperature monitor return shared by analog quads 8 and 9 analog quad av9 1 input analog quad 9 analog quad ac9 1 input analog quad ag9 1 output analog quad at9 1 input analog quad rtcmatch 1 output match rtc rtcpsmmatch 1 output match connected to vrpsm rtc rtcxtlmode[1:0] 2 output drives xtlosc rtcmode[1:0] pins rtc rtcxtlsel 1 output drives xtlosc modesel pin rtc rtcclk 1 input rtc clock input rtc table 2-36 ? analog block pin description (continued) signal name number of bits direction function location of details
device architecture 2-84 revision 4 the third part of the analog quad is called the gate driver block, and its output pin is named ag. this section is used to drive an external fet. there are two modes available: a high current drive mode and a current source control mode. both negative and positive voltage polarities are available, and in the current source control mode, four diff erent current levels are available. the fourth section of the analog quad is called th e temperature monitor block, and its input pin name is at. this block is similar to the voltage monitor block, except that it has an addi tional function: it can be used to monitor the temperature of an external dio de-connected transistor. it has a modified prescaler and is limited to positive voltages only. the analog quad can be configured during design time by libero soc; however, the acm can be used to change the parameters of any of these i/os during runtime. this type of chang e is referred to as a context switch. the analog quad is a modular struct ure that is replicated to generate the analog i/o resources. each fusion device su pports between 5 and 10 analog quads. the analog pads are numbered to clearly identify both the type of pad (voltage, current, gate driver, or temperature pad) and its correspond ing analog quad (av0, ac0, ag0, at0, av1, ?, ac9, ag9, and at9). there are three types of input pads (avx, ac x, and atx) and one type of analog output pad (agx). since there can be up to 10 analog quads on a devic e, there can be a maximum of 30 analog input pads and 10 analog output pads. figure 2-65 ? analog quad analog quad av ac at voltage monitor block current monitor block ag prescaler prescaler prescaler digital input power mosfet gate driver current monitor/instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
fusion family of mixed signal fpgas revision 4 2-85 voltage monitor the fusion analog quad offers a robust set of voltage-monitoring capabilities unique in the fpga industry. the analog quad comprises three analog input pads? analog voltage (av), analog current (ac), and analog temperature (at)? and a single gate driver output pad, analog gate (ag). there are many common characteristics among the analog inpu t pads. each analog input can be configured to connect directly to the input mux of the adc. when configured in this manner ( figure 2-66 ), there will be no prescaling of the input signal. care must be taken in this mode not to drive the adc into saturation by applying an input voltage greater than the reference voltage. the internal reference voltage of the adc is 2.56 v. optionally, an external reference can be su pplied by the user. the external reference can be a maximum of 3.3 v dc. figure 2-66 ? analog quad direct connect prescaler prescaler prescaler analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
device architecture 2-86 revision 4 the analog quad offers a wide variety of prescali ng options to enable the adc to resolve the input signals. figure 2-67 shows the path through the analog quad for a signal that is to be prescaled prior to conversion. the adc internal reference voltage and the prescaler factors were selected to make both prescaling and postscaling of the signals easy binary calculations (refer to table 2-57 on page 2-133 for details). when an analog input pad is conf igured with a prescaler, there will be a 1 m ? resistor to ground. this occurs even when the device is in power-down mode. in low power standby or sleep mode (vcc is off, vcc33a is on, vcci is on) or when the resource is not used, analog inputs are pulled down to ground through a 1 m ? resistor. the gate driver output is float ing (or tristated), and there is no extra current on vcc33a. these scaling factors hold true whet her the particular pad is configur ed to accept a positive or negative voltage. note that whereas the av and ac pads support the same prescaling factors, the at pad supports a reduced set of prescaling fact ors and supports positive voltages only. typical scaling factors are given in table 2-57 on page 2-133 , and the gain error (which contributes to the minimum and maximum) is in table 2-49 on page 2-120 . figure 2-67 ? analog quad prescaler input configuration prescaler prescaler prescaler analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
fusion family of mixed signal fpgas revision 4 2-87 terminology bw ? bandwidth bw is a range of frequencies that a channel can handle. channel a channel is define as an analog input configured as one of the prescaler range shown in table 2-57 on page 2-133 . the channel includes the prescaler circuit and the adc. channel gain channel gain is a measured of the deviation of the actual slope from the ideal slope. the slope is measured from the 20% and 80% point. eq 1 channel gain error channel gain error is a deviation from the ideal slope of the transfer function. the prescaler gain error is expressed as the percent difference between the actual and ideal, as shown in eq 2 . eq 2 channel input offset error channel offset error is measured as the input voltage that causes the transition from zero to a count of one. an ideal prescaler will have offset equal to ? of lsb voltage. offset error is a positive or negative when the first transition point is higher or lower t han ideal. offset error is expressed in lsb or input voltage. total channel error total channel error is defined as the total error measured compared to the ideal value. total channel error is the sum of gain erro r and offset error combined. figure 2-68 shows how total channel error is measured. total channel error is defined as the difference be tween the actual adc output and ideal adc output. in the example shown in figure 2-68 , the total channel error would be a negative number. figure 2-68 ? total channel error example gain gain actual gain ideal ------------------------ - = error gain (1-gain) 100% ? = adc output code ideal output input voltage to prescaler total c hannel error c hannel gain actual output channel input offset error }
device architecture 2-88 revision 4 direct digital input the av, ac, and at pads can also be configured as high-voltage digital inputs ( figure 2-69 ). as these pads are 12 v?tolerant, the digital input can also be up to 12 v. however, the frequency at which these pads can operate is limited to 10 mhz. to enable one of these analog input pads to operate as a digital input, its corresponding digital input enable (dena xy ) pin on the analog block must be pulled high, where x is either v, c, or t (for av, ac, or at pads, respectively) and y is in the range 0 to 9, correspon ding to the appropriate analog quad. when the pad is configured as a digital input, the si gnal will come out of the analog block macro on the appropriate da x out y pin, where x represents the pad type (v for av pad, c for ac pad, or t for at pad) and y represents the appropriate anal og quad number. example: if the at pad in analog quad 5 is configured as a digital input, it will come out on the datout5 pin of the analog block macro. figure 2-69 ? analog quad direct digital input configuration analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx) prescaler prescaler prescaler
fusion family of mixed signal fpgas revision 4 2-89 current monitor the fusion analog quad is an excellent element for voltage- and current-monitoring applications. in addition to supporting the same f unctionality offered by the av pad, the ac pad can be configured to monitor current across an external sense resistor ( figure 2-70 ). to support this cu rrent monitor function, a differential amplifier with 10x gain passes the am plified voltage drop between the av and ac pads to the adc. the amplifier enables the us er to use very small resistor va lues, thereby limiting any impact on the circuit. this function of the ac pad does no t limit av pad operation. the av pad can still be configured for use as a direct voltage input or scale d through the av prescaler independently of it?s use as an input to the ac pad?s differential amplifier. figure 2-70 ? analog quad current monitor configuration prescaler prescaler prescaler analog quad av ac at voltage monitor block current monitor block ag power digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx)
device architecture 2-90 revision 4 to initiate a current measuremen t, the appropriate current monitor strobe (cmstb) signal on the ab macro must be asserted low for at least t cmslo in order to discharge the previous measurement. then cmstb must be asserted high for at least t cmset prior to asserting the adcstart signal. the cmstb must remain high until after the sample signal is de-asserted by the ab macro. note that the minimum sample time cannot be less than t cmshi . figure 2-71 shows the timing diagram of cmstb in relationship with the adc control signals. figure 2-72 illustrates positive current m onitor operation. the differential voltage between av and ac goes into the 10 amplifier and is then converted by the adc. for example, a current of 1.5 a is drawn from a 10 v supply and is measured by the voltage drop across a 0.050 ? sense resistor, the voltage drop is amplified by ten times by the amplifier and then measured by the adc. the 1.5 a current creates a differential voltage across the sense resistor of 75 mv. this becomes 750 mv after amplification. thus, the adc measures a current of 1.5 a as 750 mv. us ing an adc with 8-bit resolution and varef of 2.56 v, the adc result is decimal 75. eq 3 shows how to compute the cu rrent from the adc result. eq 3 where i is the current flowing through the sense resistor adc is the result from the adc varef is the reference voltage n is the number of bits rsense is the resistance of the sense resistor figure 2-71 ? timing diagram for cu rrent monitor strobe vadc t cmset cmstbx adcstart can be asserted after this point to start adc sampling. t cmshi adcstart t cmslo i adc v aref ? ?? 10 2 n ? r sense ? ?? ? =
fusion family of mixed signal fpgas revision 4 2-91 care must be taken when choosing the right resist or for current measuremen t application. note that because of the 10 amplification, the maximum measurable difference between the av and ac pads is v aref / 10. a larger av-to-ac voltage drop will result in adc saturation; that is, the digital code put out by the adc will stay fixed at the full scale value. theref ore, the user must select the external sense resistor appropriately. table 2-38 shows recommended resistor values fo r different current measurement ranges. when choosing resistor values for a system, there is a trade-off between measurement accuracy and power consumption. choosing a large resistor will increase the voltage drop and hence increase accuracy of the measurement; however the larger voltage drop dissipates more power (p = i 2 r). the current monitor is a unipolar system, meaning that the differential voltage swing must be from 0 v to v aref /10. therefore, the current monitor only supports differential voltage where |v av -v ac | is greater than 0 v. this results in the requirement that the pot ential of the av pad must be larger than the potential of the ac pad. this is straightforward for pos itive voltage systems. for a negative voltage system, it means that the av pad must be "more negat ive" than the ac pad. this is shown in figure 2-73 . in this case, both the av pad and the ac pad are co nfigured for negative operatio ns and the output of the differential amplifier still falls between 0 v and v aref as required . figure 2-72 ? positive current monitor 0-12 v r sense i acx avx cmstbx 10 x current monitor vadc to analog mux (refer table 2-3 6 for mux chann el number)
device architecture 2-92 revision 4 terminology accuracy the accuracy of fusion current monitor is 2 mv mini mum plus 5% of the differential voltage at the input. the input accuracy can be translate d to error at the adc output by using eq 4 . the 10 v/v gain is the gain of the current monitor circuit, as described in the "current monitor" section on page 2-89 . for 8- bit mode, n = 8, v aref = 2.56 v, zero differential voltage between av and ac, the error ( e adc ) is equal to 2 lsbs. eq 4 where n is the number of bits v aref is the reference voltage v av is the voltage at av pad v ac is the voltage at ac pad table 2-37 ? recommended resistor for different current range measurement current range recommended minimum resistor value (ohms) > 5 ma ? 10 ma 10 ? 20 > 10 ma ? 20 ma 5 ? 10 > 20 ma ? 50 ma 2.5 ? 5 > 50 ma ? 100 ma 1 ? 2 > 100 ma ? 200 ma 0.5 ? 1 > 200 ma ? 500 ma 0.3 ? 0.5 > 500 ma ? 1 a 0.1 ? 0.2 > 1 a ? 2 a 0.05 ? 0.1 > 2 a ? 4 a 0.025 ? 0.05 > 4 a ? 8 a 0.0125 ? 0.025 > 8 a ? 12 a 0.00625 ? 0.02 figure 2-73 ? negative current monitor i r sense 0 to ?10.5 v avx acx cmstbx 10 x vadc current monitor to analog mux (see table 2-36 for muxchannel number) e adc 2 mv 0.05 v av v ac ? + ?? 10 v ?? v ? ? 2 n v aref ----------------- ? =
fusion family of mixed signal fpgas revision 4 2-93 gate driver the fusion analog quad includes a gate driv er connected to the quad's ag pin ( figure 2-74 ). designed to work with external p- or n-channel mosf ets, the gate driver is a configurable current sink or source and requires an external pull-up or pull-dow n resistor. the ag supports 4 selectable gate drive levels: 1 a, 3 a, 10 a, and 30 a ( figure 2-75 on page 2-94 ). the ag also supports a high current drive mode in which it can sink 20 ma; in this mo de the switching rate is approximately 1.3 mhz with 100 ns turn-on time and 600 ns turn-off time. modele d on an open-drain-style ou tput, it does not output a voltage level without an appropriat e pull-up or pull-down resistor. if 1 v is forced on the drain, the current sinking/sourcing will exceed the ability of the transistor, and the device could be damaged. the ag pad is turned on via the corresponding gdon x pin in the analog block macro, where x is the number of the corresponding analog quad for the ag pad to be enabled (gdon0 to gdon9). the gate-to-source voltage (v gs ) of the external mosfet is limit ed to the programmable drive current times the external pull-up or pull-down resistor value ( eq 5 ). v gs ? i g (r pullup or r pulldown ) eq 5 the rate at which the gate voltage of the extern al mosfet slews is determined by the current, i g , sourced or sunk by the ag pin and the gate-to-source capacitance, c gs , of the external mosfet. as an approximation, the slew rate is given by eq 6 . dv/dt = i g / c gs eq 6 figure 2-74 ? gate driver analog quad av ac at voltage monitor block current monitor block ag power line side load side digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip r pullup from fpga (gdonx) prescaler prescaler prescaler
device architecture 2-94 revision 4 c gs is not a fixed capacitance but, depending on the circuitry connected to its drain terminal, can vary significantly during the course of a tu rn-on or turn-off transient. thus, eq 6 on page 2-93 can only be used for a first-order estimate of the switching speed of the external mosfet. figure 2-75 ? gate driver example ag high current high current 1 a3 a 10 a 30 a 1 a3 a 10 a 30 a
fusion family of mixed signal fpgas revision 4 2-95 temperature monitor the final pin in the analog quad is the analog temperat ure (at) pin. the at pin is used to implement an accurate temperature monitor in conjunction with an external diode-connected bipolar transistor ( figure 2-76 ). for improved temperature m easurement accuracy, it is important to use the atrtn pin for the return path of the current sourced by the at pin. each atrtn pin is shared between two adjacent analog quads. additionally, if not us ed for temperature monitoring, the at pin can provide functionality similar to that of the av pad. however, in this mode only positive voltages can be applied to the at pin, and only two prescaler factors are available (16 v and 4 v ranges?refer to table 2-57 on page 2-133 ). figure 2-76 ? temperature monitor quad analog quad av ac at voltage monitor block current monitor block ag digital input power mosfet gate driver current monitor / instr amplifier temperature monitor digital input digital input pads to analog mux to analog mux to analog mux to fpga (davoutx) to fpga (dacoutx) to fpga (datoutx) on-chip gate driver temperature monitor block off-chip from fpga (gdonx) prescaler prescaler prescaler atrtn discrete bipolar transistor
device architecture 2-96 revision 4 fusion uses a remote diode as a temperature sensor. the fusi on temperature monitor uses a differential input; the at pin and atrtn (at return) pin are the differential inputs to the temperature monitor. there is one temperature monitor in ea ch quad. a simplified block diagram is shown in figure 2-77 . the fusion approach to measuring temperature is forcing two different currents through the diode with a ratio of 10:1. the switch that controls the differ ent currents is controlled by the temperature monitor strobe signal, tmstb. setting tmstb to '1' will initiate a temperature reading. the tmstb should remain '1' until the adc finishes sampling the vo ltage from the temperature monitor. the minimum sample time for the temperature monitor cannot be less than the minimum strobe high time minus the setup time. figure 2-78 shows the timing diagram. note: when the ieee 1149.1 boundary scan extest in struction is executed , the ag pad drive strength ceases and becomes a 1 a sink into the fusion device. figure 2-77 ? block diagram for temper ature monitor circuit figure 2-78 ? timing diagram for the temper ature monitor strobe signal tmstbx vdd33a atrtnxy atx 12.5 x ? v to analog mux (refer table 2-36 for mux channel number) vadc 100 a 10 a + ? + ? vadc tmstbx adc should start sampling at this point adcstart t tmslo t tmshi t tmsset
fusion family of mixed signal fpgas revision 4 2-97 the diode?s voltage is measured at each current le vel and the temperature is calculated based on eq 7 . eq 7 where i tmslo is the current when the temperature strobe is low, typically 100 a i tmshi is the current when the temperature strobe is high, typically 10 a v tmslo is diode voltage while temperature strobe is low v tmshi is diode voltage while temperature strobe is high n is the non-ideality factor of the diode-connected transistor. it is typically 1.004 for the microsemi- recommended transistor type 2n3904. k = 1.3806 x 10 -23 j/k is the boltzman constant q = 1.602 x 10 -19 c is the charge of a proton when i tmslo / i tmshi = 10, the equation can be simplified as shown in eq 8 . eq 8 in the fusion tmb, the ideality factor n for 2n3904 is 1.004 and ? v is amplified 12.5 times by an internal amplifier; hence the voltage before entering the adc is as given in eq 9 . eq 9 this means the temperature to voltage relationsh ip is 2.5 mv per degree kelvin. the unique design of fusion has made the temperature monitor system simple for the user. when the 10-bit mode adc is used, each lsb represents 1 degree kelvin, as shown in eq 10 . that is, e. 25c is equal to 293k and is represented by decimal 2 93 counts from the adc. eq 10 if 8-bit mode is used for the adc resolution, each lsb represents 4 degrees kelvin; however, the resolution remains as 1 degree kelvin per lsb, ev en for 12-bit mode, due to the temperature monitor design. an example of the temperature dat a format for 10-bit mode is shown in ta b l e 2 - 3 8 . table 2-38 ? temperature data format temperature temperature (k) digital output (adc 10-bit mode) ?40c 233 00 1110 1001 ?20c 253 00 1111 1101 0c 273 01 0001 0001 1c 274 01 0001 0010 10 c 283 01 0001 1011 25c 298 01 0010 1010 50 c 323 01 0100 0011 85 c 358 01 0110 0110 v tmslo v tmshi ? n kt q ------ - ln i tmslo i tmshi ----------------- ?? ?? = ? vv tmslo v tmshi ? 1.986 10 4 ? ? nt == v adc ? v 12.5 ? 2.5 mv kt ? ?? ? == 1 k 2.5 mv 2 10 2.56 v ---------------- - ? 1 lsb ==
device architecture 2-98 revision 4 terminology resolution resolution defines the smallest te mperature change fusion temperature monitor can resolve. for adc configured as 8-bit mode, each lsb represents 4 c, and 1c per lsb for 10-bi t mode. with 12-bit mode, the temperature monitor can still only reso lve 1c due to temperature monitor design. offset the fusion temperature monitor has a systematic offset ( table 2-49 on page 2-120 ), excluding error due to board resistance and ideality factor of the external diode. microsemi provides an ip block (calibip) that is required in order to mitigate the systematic temp erature offset. for further details on calibip, refer to the " temperature, voltage, and current calib ration in fusion fpgas" chapter of the fusion fpga fabric user's guide .
fusion family of mixed signal fpgas revision 4 2-99 analog-to-digital converter block at the heart of the fusion analog system is a progra mmable successive approximation register (sar) adc. the adc can support 8-, 10-, or 12-bit modes of operation. in 12-bit mode, the adc can resolve 500 ksps. all results are msb-justifie d in the adc. the input to the adc is a large 32:1 analog input multiplexer. a simplified block diagram of the analog quads, analog input multiplexer, and adc is shown in figure 2-79 . the adc offers multiple self-calibrating modes to ensure consistent high performance both at power-up and during runtime. figure 2-79 ? adc block diagram adc 12 analog mux (32 to 1) temperature monitor pads internal diode digital output to fpga av0 ac0 ag0 at0 av1 ac1 ag1 at1 av2 ac2 ag2 at2 av3 ac3 ag3 at3 av4 ac4 ag4 at4 av5 ac5 ag5 at5 av6 ac6 ag6 at6 av7 ac7 ag7 at7 av8 ac8 ag8 at8 av9 ac9 ag9 at9 atreturn89 atreturn67 atreturn45 atreturn23 atreturn01 analog quad 0 analog quad 4 analog quad 5 analog quad 6 analog quad 7 analog quad 8 analog quad 9 analog quad 3 analog quad 2 analog quad 1 v cc (1.5 v) 0 1 31 these are hardwired connections within analog quad. chnumber[4:0]
device architecture 2-100 revision 4 adc description the fusion adc is a 12-bit sar adc. it offers a wide variety of features for different use models. figure 2-80 shows a block diagram of the fusion adc. ? configurable resolution: 8-bit, 10-bit, and 12-bit mode ? dnl: 0.6 lsb for 10-bit mode ? inl: 0.4 lsb for 10-bit mode ? no missing code ? internal varef = 2.56 v ? maximum sample rate = 600 ksps ? power-up calibration and dynamic calibration afte r every sample to compensate for temperature drift over time adc theory of operation an analog-to-digital converter is used to capture discrete samples of a continuous analog voltage and provide a discrete binary representation of the si gnal. analog-to-digital converters are generally characterized in three ways: ? input voltage range ? resolution ? bandwidth or conversion rate the input voltage range of an adc is determined by its reference voltage (vref). fusion devices include an internal 2.56 v reference, or the user can supply an external reference of up to 3.3 v. the following examples use the internal 2.56 v reference, so the full-scale input range of the adc is 0 to 2.56 v. the resolution (lsb) of the adc is a function of th e number of binary bits in the converter. the adc approximates the value of the input voltage using 2n step s, where n is the number of bits in the converter. each step therefore represents vref 2n volts. in the case of the fusion adc configured for 12-bit operation, the lsb is 2.56 v / 4096 = 0.625 mv. finally, bandwidth is an indication of the maximum number of conversions the adc can perform each second. the bandwidth of an adc is constrained by its architecture and several key performance characteristics. figure 2-80 ? adc simplified block diagram tvc sysclk adcclk signals from analog quads chnumber sar adc stc mode result datavalid busy status sample calibrate varef analog mux 32 12
fusion family of mixed signal fpgas revision 4 2-101 there are several popular adc architectures, each with advantages and limitations. the analog-to-digital converter in fusion devices is a switched-capacitor successive approximation register (sar) adc. it supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per second (ksps). built-in bandgap circuitry offers 1% internal voltage reference accuracy or an external reference voltage can be used. as shown in figure 2-81 , a sar adc contains n capacitors with binary-weighted values. to begin a conversion, all of the capacitors are quickly discharged. then vin is applied to all the capacitors for a period of time (acquisition time) during which the capacitors are charged to a value very close to vin. then all of the capacitors are sw itched to ground, and thus ?vin is applied across the comparator. now the conversion process begins. first, c is switched to vref . because of the binary weighting of the capacitors, the voltage at th e input of the comparator is then shown by eq 11 . voltage at input of compar ator = ?vin + vref / 2 eq 11 if vin is greater than vref / 2, t he output of the comparator is 1; otherwise, the comparator output is 0. a register is clocked to retain this value as the m sb of the result. next, if the msb is 0, c is switched back to ground; otherwise, it remains connected to vr ef, and c / 2 is connected to vref. the result at the comparator input is now either ?vin + vref / 4 or ?vin + 3 vref / 4 (depending on the state of the msb), and the comparator output now indicates the va lue of the next most significant bit. this bit is likewise registered, and the process continues for eac h subsequent bit until a conversion is completed. the conversion process requires so me acquisition time plus n + 1 adc clock cycles to complete. figure 2-81 ? example sar adc architecture comparator c c / 2 c / 4 c / 2 n?2 c / 2 n?1 vref vin
device architecture 2-102 revision 4 this process results in a binary approximation of vin. generally, there is a fixed interval t, the sampling period, between the samples. the inverse of the sampling period is often referred to as the sampling frequency f s = 1 / t. the combined effect is illustrated in figure 2-82 . figure 2-82 demonstrates that if the signal changes fast er than the sampling rate can accommodate, or if the actual value of vin falls between counts in the result, this information is lost during the conversion. there are several techniques that can be used to address these issues. first, the sampling rate must be chosen to provid e enough samples to adequately represent the input signal. based on the nyquist-shannon sampling theorem, the minimum sampling rate must be at least twice the frequency of the highest frequency compon ent in the target signal (nyquist frequency). for example, to recreate the frequen cy content of an audio signal with up to 22 khz bandwidth, the user must sample it at a minimum of 44 ksps. however, as shown in figure 2-82 , significant post-processing of the data is required to interpolate the value of the waveform during the time between each sample. similarly, to re-create the amplit ude variation of a signal, the signal must be sampled with adequate resolution. continuing with the audio example, the dynamic range of the human ear (the ratio of the amplitude of the threshold of hearing to the threshold of pain) is generally accepted to be 135 db, and the dynamic range of a typical symphony orchestra performance is around 85 db. most commercial recording media provide about 96 db of dynamic range using 16-bit sample resolution. but 16-bit fidelity does not necessarily mean that you need a 16-bit adc. as long as the input is sampled at or above the nyquist frequency, post-processing techniques can be used to interpolate intermediate values and reconstruct the original input signal to within desired tolerances. if sophisticated digital signal processing (dsp) capabili ties are available, the best results are obtained by implementing a reconstruction filter, which is used to interpolate many intermediate values with higher resolution than the original data. interpolating many intermediate values increases the effective number of samples, and higher resolution increases the effe ctive number of bits in the sample. in many cases, however, it is not cost-effective or necessary to im plement such a sophisticated reconstruction algorithm. for applications that do not require extremely fine re production of the input signal, alternative methods can enhance digital sampling results with relative ly simple post-processing. the details of such techniques are out of the scope of this chapter; refer to the improving adc results through oversampling and post-processing of data white paper for more information. figure 2-82 ? conversion example t lsb
fusion family of mixed signal fpgas revision 4 2-103 adc terminology conversion time conversion time is the interval between the release of the hold state (imposed by the input circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one lsb of a new input value. dnl ? differential non-linearity for an ideal adc, the analog-input levels that trig ger any two successive output codes should differ by one lsb (dnl = 0). any deviation from one lsb in defined as dnl ( figure 2-83 ). enob ? effective number of bits enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc?s error consists only of quantization of no ise. as the input frequen cy increases, the overall noise (particularly in the distortion components) al so increases, thereby r educing the enob and sinad (also see ?signal-to-noise and distortion ratio (sin ad)?.) enob for a full-scale, sinusoidal input waveform is computed using eq 12 . eq 12 fs error ? full-scale error full-scale error is the difference between the actual valu e that triggers that tran sition to full-scale and the ideal analog full-scale transition value. full-sca le error equals offset error plus gain error. figure 2-83 ? differential non-linearity (dnl) adc output code input voltage to prescaler error = ?0.5 lsb error = +1 lsb ideal output actual output enob sinad 1.76 ? 6.02 ------------------------------------ - =
device architecture 2-104 revision 4 gain error the gain error of an adc indicates how well the slope of an actual transfer function matches the slope of the ideal transfer function. gain error is usually expressed in lsb or as a percent of full-scale (%fsr). gain error is the full-scale error minus the offset error ( figure 2-84 ). gain error drift gain-error drift is the variation in gain error due to a change in ambient temper ature, typically expressed in ppm/c. figure 2-84 ? gain error adc output code input voltage to prescaler ideal output actual output gain = 2 lsb 1...11 0...00 fs voltage
fusion family of mixed signal fpgas revision 4 2-105 inl ? integral non-linearity inl is the deviation of an actual transfer function fr om a straight line. after nullifying offset and gain errors, the straight line is either a best-fit strai ght line or a line drawn between the end points of the transfer function ( figure 2-85 ). lsb ? least significant bit in a binary number, the lsb is the least weighted bit in the group. typically, the lsb is the furthest right bit. for an adc, the weight of an lsb equals the fu ll-scale voltage range of the converter divided by 2 n , where n is the converter?s resolution. eq 13 shows the calculation for a 10-bit adc with a unipolar full-scale voltage of 2.56 v: 1 lsb = (2.56 v / 2 10 ) = 2.5 mv eq 13 no missing codes an adc has no missing codes if it produces all possible digital codes in response to a ramp signal applied to the analog input. offset error offset error indicates how well the actual transfer function matches the ideal tr ansfer function at a single point. for an ideal adc, the first tr ansition occurs at 0.5 lsb above ze ro. the offset voltage is measured by applying an analog input such that the adc outputs all zeroes and increases until the first transition occurs ( figure 2-86 on page 2-106 ). figure 2-85 ? integral non-linearity (inl) adc output code input voltage to prescaler inl = +0.5 lsb inl = +1 lsb ideal output actual output
device architecture 2-106 revision 4 resolution adc resolution is the number of bits used to represent an analog input signal. to more accurately replicate the analog signal, reso lution needs to be increased. sampling rate sampling rate or sample frequency, specified in samples per second (sps), is the rate at which an adc acquires (samples) the analog input. snr ? signal-to-noise ratio snr is the ratio of the amplitude of the desired signa l to the amplitude of the noise signals at a given point in time. for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr ( eq 14 ) is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum adc noise is caused by quantization error only and results directly from the adc?s resolution (n bits): eq 14 sinad ? signal-to-noise and distortion sinad is the ratio of the rms amplitude to the mean va lue of the root-sum-square of the all other spectral components, including harmonics, but excluding dc. sinad is a good indication of the overall dynamic performance of an adc because it includes all components which make up noise and distortion. total harmonic distortion thd measures the distortion content of a signal, and is specified in decibels relative to the carrier (dbc). thd is the ratio of the rms sum of the selected harm onics of the input signal to the fundamental itself. only harmonics within the nyquist limit are included in the measurement. figure 2-86 ? offset error adc output code input voltage to prescaler ideal output offset error = 1.5 lsb actual output 0...00 0...01 snr db[max] 6.02 db n 1.76 db + ? =
fusion family of mixed signal fpgas revision 4 2-107 tue ? total unadjusted error tue is a comprehensive specification that includes linearity errors, gain error, and offset error. it is the worst-case deviation from the ideal device perf ormance. tue is a st atic specification ( figure 2-87 ). adc operation once the adc has powered up and been released from reset, adcreset, the adc will initiate a calibration routine designed to provide optimal adc performance. the fusion adc offers a robust calibration scheme to reduce integr ated offset and linearity errors. the of fset and linearity errors of the main capacitor array are compensated for with an 8- bit calibration capacitor array. the offset/linearity error calibration is carried out in two ways. first, a power-up calibration is carried out when the adc comes out of reset. this is initiated by the calibr ate output of the analog block macro and is a fixed number of adc_clk cycles (3, 840 cycles), as shown in figure 2-89 on page 2-114 . in this mode, the linearity and offset errors of th e capacitors are calibrated. to further compensate for drift and temperature-depend ent effects, every conversion is followed by post- calibration of either the offset or a bit of the main capacitor array. the post-calibration ensures that, over time and with temperature, the adc remains consistent. after both calibration and the setting of the approp riate configurations, as explained above, the adc is ready for operation. setting the adcstart signal hi gh for one clock period will initiate the sample and conversion of the analog signal on the channel as configured by chnumber[4:0]. the status signals sample and busy will show when the adc is sampling and converting ( figure 2-91 on page 2-115 ). both sample and busy will initially go high. after the adc has sampled and held the analog signal, sample will go low. after the entire operation has co mpleted and the analog signal is converted, busy will go low and datavalid will go high. this indicates that the digital result is available on the result[11:0] pins. datavalid will remain high until a subsequent adc_start is issued. the datavalid goes low on the rising edge of sysc lk as shown in figure 2-90 on page 2-114 . the result signals will be kept constant until the adc finishes the subsequent sample. the next sampled result will be available when datavalid goes high again. it is ideal to read the result when datavalid is '1'. the result is latched and remains unchanged until the next datavlaid rising edge. figure 2-87 ? total unadjusted error (tue) adc output code input voltage to prescaler ideal output tue = 0.5 lsb
device architecture 2-108 revision 4 adc input multiplexer at the input to the fusion adc is a 32:1 multiple xer. of the 32 input channels, up to 30 are user definable. two of these channels are hardwired internally. channel 31 connects to an internal temperature diode so the temperatur e of the fusion device itself can be monitored. channel 0 is wired to the fpga?s 1.5 v vcc supply, enabling the fusion device to monitor its own power supply. doing this internally makes it unnecessary to use an analog i/o to support these functions. the balance of the mux inputs are connected to analog quads (see the "analog quad" section on page 2-83 ). ta b l e 2 - 4 0 defines which analog quad inputs are associated with which specific analog mux channels. the number of analog quads present is device-dependent; refer to the family list in the "fusion family" table on page i of this datasheet for the number of quads per device . regardless of the number of quads populated in a device, the internal connections to both vcc and the internal temperature diode remain on channels 0 and 31, respectively. to sample the internal temperat ure monitor, it must be strobed (similar to the at pads). the tmstbint pin on the analog block macro is the control for strobing the internal temperature measurement diode. to determine which channel is selected for conversion, there is a five-pin interface on the analog block, chnumber[4:0], defined in ta b l e 2 - 3 9 . table 2-40 shows the correlation between the analog mux input channels and the analog input pins. table 2-39 ? channel selection channel number chnumber[4:0] 0 00000 1 00001 2 00010 3 00011 . . . . . . 30 11110 31 11111 table 2-40 ? analog mux channels analog mux channel signal analog quad number 0 vcc_analog 1 av0 analog quad 0 2ac0 3at0 4 av1 analog quad 1 5ac1 6at1 7 av2 analog quad 2 8ac2 9at2 10 av3 analog quad 3 11 ac3 12 at3 13 av4 analog quad 4 14 ac4 15 at4
fusion family of mixed signal fpgas revision 4 2-109 the adc can be powered down independently of the fp ga core, as an additional control or for power- saving considerations, via the pwrdwn pin of the analog block. the pwrdwn pin controls only the comparators in the adc. adc modes the fusion adc can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion, and dynamic calibration. this is cont rolled by mode[3:0], as defined in table 2-41 on page 2-109 . the output of the adc is the result[11:0] sign al. in 8-bit mode, the most significant 8 bits result[11:4] are used as the adc value and the least significant 4 bits result[3:0] are logical '0's. in 10-bit mode, result[11:2] are used the adc value and result[1:0] are logical 0s. integrated voltage reference the fusion device has an integrated on-chip 2.56 v reference voltage for the adc. the value of this reference voltage was chosen to make the prescaling and postscaling factors for the prescaler blocks change in a binary fashion. however, if desired, an external reference voltage of up to 3.3 v can be 16 av5 analog quad 5 17 ac5 18 at5 19 av6 analog quad 6 20 ac6 21 at6 22 av7 analog quad 7 23 ac7 24 at7 25 av8 analog quad 8 26 ac8 27 at8 28 av9 analog quad 9 29 ac9 30 at9 31 internal temperature monitor table 2-41 ? mode bits function name bits function mode 3 0 ? internal calibration after ev ery conversion; two adcclk cycles are used after the conversion. 1 ? no calibration after every conversion mode 2 0 ? power-down after conversion 1 ? no power-down after conversion mode 1:0 00 ? 10-bit 01 ? 12-bit 10 ? 8-bit 11 ? unused table 2-40 ? analog mux channels (continued) analog mux channel signal analog quad number
device architecture 2-110 revision 4 connected between the varef and adcgndref pins. the varefsel control pin is used to select the reference voltage. adc clock the speed of the adc depends on its internal clock, adcclk, which is not accessible to users. the adcclk is derived from sysclk. input signal tvc[7: 0], time divider control, determines the speed of the adcclk in relationship to sysclk, based on eq 15 . eq 15 tvc: time divider control (0?255) t adcclk is the period of adcclk, and mu st be between 0.5 mhz and 10 mhz t sysclk is the period of sysclk the frequency of adcclk, f adcclk , must be within 0.5 hz to 10 mhz. the inputs to the adc are synchronized to sysclk . a conversion is initiated by asserting the adcstart signal on a rising edge of sysclk. figure 2-90 on page 2-114 and figure 2-91 on page 2-115 show the timing diagram for the adc. acquisition time or sample time control acquisition time (t sample ) specifies how long an analog input signal has to charge the internal capacitor array. figure 2-88 shows a simplified internal input sampling mechanism of a sar adc. the internal impedance (z inad ), external source resistance (r source ), and sample capacitor (c inad ) form a simple rc network. as a result, the accuracy of the adc can be affected if the adc is given insufficient time to charge the ca pacitor. to resolve this problem, you can either reduce the source resistance or increase the sampling time by changing the acquisition time using the stc signal. eq 16 through eq 18 can be used to calculate the acquisition time required for a given input. the stc signal gives the number of sample periods in adcclk for the acquisition time of the desired signal. if the actual acquisition time is higher than the stc value, the settling time error can affect the accuracy of the adc, because the sampling capacitor is only partia lly charged within the given sampling cycle. example acquisition times are given in table 2-44 and ta b l e 2 - 4 5 . when controlling the sample time for the adc table 2-42 ? varef bit function name bit function varef 0 reference voltage selection 0 ? internal voltage reference selected. varef pin outputs 2.56 v. 1 ? input external voltage refe rence from varef and adcgndref table 2-43 ? tvc bits function name bits function tvc [7:0] sysclk divider control figure 2-88 ? simplified sample and hold circuitry t adcclk 41tvc + ?? ? t sysclk ? = sample and hold z inad c inad r source
fusion family of mixed signal fpgas revision 4 2-111 along with the use of the active bipolar prescaler, current monitor, or temperature monitor, the minimum sample time(s) for ea ch must be obeyed. eq 19 can be used to determine the appropriate value of stc. you can calculate the minimum act ual acquisition time by using eq 16 : vout = vin(1 ? e? t/rc ) eq 16 for 0.5 lsb gain error, vout should be replaced with (vin ?(0.5 lsb value)): (vin ? 0.5 lsb value) = vin(1 ? e? t/rc ) eq 17 where vin is the adc reference voltage (vref) solving eq 17 : t = rc x ln (vin / (0.5 x lsb value)) eq 18 where r = z inad + r source and c = c inad . calculate the value of stc by using eq 19 . t sample = (2 + stc) x (1 / adcclk) or t sample = (2 + stc) x (adc clock period) eq 19 where adcclk = adc clock frequency in mhz. t sample = 0.449 s from bit resolution in table 2-44 . adc clock frequency = 10 mhz or a 100 ns period. stc = (t sample / (1 / 10 mhz)) ? 2 = 4.49 ? 2 = 2.49. you must round up to 3 to accommodate the minimum sample time. sample phase a conversion is performed in three phases. in the first phase, the analog input voltage is sampled on the input capacitor. this phase is called sample phase. during the sample phase, the output signals busy and sample change from '0' to '1', indicating the adc is busy and sampling the analog signal. the sample time can be controlled by input signals st c[7:0]. the sample time can be calculated by eq 20 . when controlling the sample time for the adc along with the use of prescaler or current monitor or temperature monitor, the minimum sample time for each must be obeyed. refer to ta b l e 2 - 4 6 o n page 2-112 and the "acquisition time or sample time control" section on page 2-110 eq 20 stc: sample time control value (0?255) t sample is the sample time table 2-44 ? acquisition time example with varef = 2.56 v vin = 2.56v, r = 4k (r source ~ 0), c = 18 pf resolution lsb value (mv) min. sa mple/hold time for 0.5 lsb (s) 8 10 0.449 10 2.5 0.549 12 0.625 0.649 table 2-45 ? acquisition time example with varef = 3.3 v vin = 3.3v, r = 4k (r source ~ 0), c = 18 pf resolution lsb value (mv) min. sa mple/hold time for 0.5 lsb (s) 8 12.891 0.449 10 3.223 0.549 12 0.806 0.649 t sample 2stc + ?? t adcclk ? =
device architecture 2-112 revision 4 sample time is computed based on the period of adcclk. distribution phase the second phase is called the dist ribution phase. during distributio n phase, the adc computes the equivalent digital value from the value stored in the input capacitor. in this phase, the output signal sample goes back to '0', indicating the sample is completed; but the busy signal remains '1', indicating the adc is still busy for distribution. the distribution time depends strictly on the number of bits. if the adc is configured as a 10-bit adc, t hen 10 adcclk cycles are needed. eq 8 describes the distribution time. eq 21 n: number of bits post-calibration phase the last phase is the post-calibration phase. this is an optional phase. the post-calibration phase takes two adcclk cycles. t he output busy signal will rema in '1' until the post-calib ration phase is completed. if the post-calibration phase is skipp ed, then the busy signal goes to '0' after distribution phase. as soon as busy signal goes to '0', the datavalid signal goes to '1', indicating the digital result is available on the result output signals. datavaild will remain '1 ' until the next adcstart is asserted. microsemi recommends enabling post-calibration to compensate for drift and temperature-dependent effects. this ensures that the adc remains consistent over time and with temperature. the post-calibration phase is enabled by bit 3 of the mode register. eq 9 describes the post-calibration time. eq 22 mode[3]: bit 3 of the mode register, described in table 2-41 on page 2-109 . the calculation for the conversion time for the adc is summarized in eq 23 . t conv = t sync_read + t sample + t distrib + t post-cal + t sync_write eq 23 t conv : conversion time t sync_read : maximum time for a signal to synchronize with sysclk. for calc ulation purposes, the worst case is a period of sysclk, t sysclk . t sample : sample time t distrib : distribution time t post-cal : post-calibration time t sync_write : maximum time for a signal to synchronize with sysclk. for calculation purposes, the worst case is a period of sysclk, t sysclk . intra-conversion performing a conversion during power-up calibrat ion is possible but should be avoided, since the performance is not guaranteed, as shown in table 2-49 on page 2-120 . this is described as intra- conversion. figure 2-92 on page 2-115 shows intra-conversion (conversion that starts during power-up calibration). injected conversion a conversion can be interrupted by another conversion. before the current conversion is finished, a second conversion can be started by issuing a pulse on signal adcstart. when a second conversion is issued before the current conversion is comple ted, the current conversion would be dropped and the adc would start the second conversi on on the rising edge of the sysclk. this is known as injected conversion. since the adc is synchr onous, the minimum time to issue a second conversion is two clock cycles of sysclk after the previous one. figure 2-93 on page 2-116 shows injected conversion table 2-46 ? stc bits function name bits function stc [7:0] sample time control t distrib nt adcclk ? = t post-cal mode 3 ?? 2t adcclk ? ?? ? =
fusion family of mixed signal fpgas revision 4 2-113 (conversion that starts before a previously started conversion is finished ). the total time for calibration still remains 3,840 adcclk cycles. adc example this example shows how to choose th e correct settings to achieve the fastest sample time in 10-bit mode for a system that runs at 66 mhz. assume the acquisition times defined in table 2-44 on page 2-111 for 10-bit mode, which gives 0.549 s as a minimum hold time. the period of sysclk: t sysclk = 1/66 mhz = 0.015 s choosing tvc between 1 and 33 will meet the maximum and minimum period for the adcclk requirement. a higher tvc leads to a higher adcclk period. the minimum tvc is chosen so that t distrib and t post-cal can be run faster. the period of adcclk with a tvc of 1 can be computed by eq 24 . eq 24 the stc value can now be computed by us ing the minimum sample/hold time from table 2-44 on page 2-111 , as shown in eq 25 . eq 25 you must round up to 3 to accommodate the minimum sample time requirement. the actual sample time, t sample , with an stc of 3, is now equal to 0.6 s, as shown in eq 26 eq 26 microsemi recommends post-calibration for temperature drift over time, so post-calibration is enabled. the post-calibration time, t post-cal , can be computed by eq 27 . the post-calibration time is 0.24 s. eq 27 the distribution time, t distrib , is equal to 1.2 s and c an be computed as shown in eq 28 (n is number of bits, referring back to eq 8 on page 2-97 ). eq 28 the total conversion time can now be summated, as shown in eq 29 (referring to eq 23 on page 2-112 ). t sync_read + t sample + t distrib + t post-cal + tsync_write = (0.015 + 0.60 + 1.2 + 0.24 + 0.015) s = 2.07 s eq 29 the optimal setting for the system running at 66 mhz with an adc for 10-bit mode chosen is shown in table 2-47 : table 2-47 ? optimal setting at 66 mhz in 10-bit mode tvc[7:0] = 1 = 0x01 stc[7:0] = 3 = 0x03 mode[3:0] = b'0100 = 0x4* note: no power-down after every conversion is chosen in this case; however, if the application is power-sensitive, the mode[2] can be set to '0', as described above, and it will not affect any performance. t adcclk 41tvc + ?? ? t sysclk ? 411 + ?? ? 0.015 s ? 0.12 s === stc t sample t adcclk -------------------- 2 ? 0.549 s 0.12 s ---------------------- - 2 ? 4.575 2 ? 2.575 == == t sample 2stc + ?? t adcclk ? 23 + ?? t adcclk ? 5 0.12 s ? 0.6 s ==== t post-cal 2t adcclk ? 0.24 s == t distrib nt adcclk ? 10 0.12 ? 1.2 s ===
device architecture 2-114 revision 4 timing diagrams note: *refer to eq 15 on page 2-110 for the calculation on the period of adcclk, t adcclk . figure 2-89 ? power-up calibration status signal timing diagram figure 2-90 ? input setup time sysclk adcreset calibrate t remclr t ck2qcal t ck2qcal tvc[7:0] t sutvc t hdtvc t cal = 3,840 t adcclk * t recclr sysclk adcstart t minsysclk t mpwsysclk t hdadcstart t suadcstart mode[3:0] tvc[7:0] stc[7:0] varef c hnumber[7:0] t sumode t sutvc t sustc t suchnum t suvarefsel t hdmode t hdtvc t hdstc t hdvarefsel t hdchnum
fusion family of mixed signal fpgas revision 4 2-115 standard conversion intra-conversion notes: 1. refer to eq 20 on page 2-111 for the calculation on the sample time, t sample . 2. see eq 23 on page 2-112 for calculation of the conversion time, t conv . 3. minimum time to issue an adcstart after datavalid is 1 sysclk period figure 2-91 ? standard conversion status signal timing diagram sysclk adcstart busy sample datavalid t hdadcstart t suadcstart t ck2qbusy t ck2qsample t ck2qval t sample 1 t conv 2 adc_result[11:0] t clk2result 1 st sample result t ck2qval 2 nd sample result t data2start 3 note: *t conv represents the conversion time of the second conversion. see eq 23 on page 2-112 for calculation of the conversion time, t conv . figure 2-92 ? intra-conversion timing diagram sysclk adcstart busy sample datavalid t ck2qsample t ck2qsample t ck2qval t conv * t clr2qval t ck2qbusy adcreset calibrate t ck2qcal t ck2qcal interrupts power-up calibration resumes power-up calibration
device architecture 2-116 revision 4 injected conversion note: *see eq 23 on page 2-112 for calculation on the conversion time, t conv . figure 2-93 ? injected conversion timing diagram sysclk adcstart busy sample datavalid t ck2qsample t ck2qval t conv * 1st conversion 1st start 2nd start 1st conversion cancelled, 2nd conversion t ck2qval t ck2qbusy t ck2qsample
fusion family of mixed signal fpgas revision 4 2-117 adc interface timing table 2-48 ? adc interface timing commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t sumode mode pin setup time 0.56 0.64 0.75 ns t hdmode mode pin hold time 0.26 0.29 0.34 ns t sutvc clock divide control (tvc) setup time 0.68 0.77 0.90 ns t hdtvc clock divide control (tvc) hold time 0.32 0.36 0.43 ns t sustc sample time control (stc) setup time 1.58 1.79 2.11 ns t hdstc sample time control (stc) hold time 1.27 1.45 1.71 ns t suvarefsel voltage reference select (varefsel) setup time 0.00 0.00 0.00 ns t hdvarefsel voltage reference select (varefsel) hold time 0.67 0.76 0.89 ns t suchnum channel select (chnumber) setup time 0.90 1.03 1.21 ns t hdchnum channel select (chnumber) hold time 0.00 0.00 0.00 ns t suadcstart start of conversion (adcstart) setup time 0.75 0.85 1.00 ns t hdadcstart start of conversion (adcstart) hold time 0.43 0.49 0.57 ns t ck2qbusy busy clock-to-q 1.33 1.51 1.78 ns t ck2qcal power-up calibration clock-to-q 0.63 0.71 0.84 ns t ck2qval valid conversion result clock-to-q 3.12 3.55 4.17 ns t ck2qsample sample clock-to-q 0.22 0.25 0.30 ns t ck2qresult conversion result clock-to-q 2.53 2.89 3.39 ns t clr2qbusy busy clear-to-q 2.06 2.35 2.76 ns t clr2qcal power-up calibration clear-to-q 2.15 2.45 2.88 ns t clr2qval valid conversion result clear-to-q 2.41 2.74 3.22 ns t clr2qsample sample clear-to-q 2.17 2.48 2.91 ns t clr2qresult conversion result clear-to-q 2.25 2.56 3.01 ns t recclr recovery time of clear 0.00 0.00 0.00 ns t remclr removal time of clear 0.63 0.72 0.84 ns t mpwsysclk clock minimum pulse width for the adc 4.00 4.00 4.00 ns t fmaxsysclk clock maximum frequency for the adc 100.00 100.00 100.00 mhz
device architecture 2-118 revision 4 typical performance characteristics figure 2-94 ? temperature error figure 2-95 ? effect of external sensor capacitance 0 0.5 1 1.5 2 2.5 3 3.5 ?40 10 60 110 temperature errror vs. die temperature temperature error (c) temperature (c) temperature error vs. interconnect capacitance -7 -6 -5 -4 -3 -2 -1 0 1 0 500 1000 1500 2000 capacitance (pf ) temperature error (c)
fusion family of mixed signal fpgas revision 4 2-119 figure 2-96 ? temperature reading noise when averaging is used 0 2 4 6 8 10 12 temperature reading noise rms vs. averaging number of averages noise rms (c) 1 10 100 1000 10000
device architecture 2-120 revision 4 analog system characteristics table 2-49 ? analog channel specifications commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: vcc33a = 3.3 v, vcc = 1.5 v parameter description condition min. typ. max. units voltage monitor using analog pads av, ac and at (using prescaler) input voltage (prescaler) refer to table 3-2 on page 3-3 vinap uncalibrated gain and offset errors refer to table 2-51 on page 2-125 calibrated gain and offset errors refer to table 2-52 on page 2-126 bandwidth1 100 khz input resistance refer to table 3-3 on page 3-4 scaling factor prescaler modes ( table 2-57 on page 2-133 ) sample time 10 s current monitor using an alog pads av and ac vrsm 1 maximum differential input voltage varef / 10 mv resolution refer to "current monitor" section common mode range ? 10.5 to +12 v cmrr common mode rejection ratio dc ? 1 khz 60 db 1 khz - 10 khz 50 db > 10 khz 30 db t cmshi strobe high time adc conv. time 200 s t cmshi strobe low time 5 s t cmshi settling time 0.02 s accuracy input differential voltage > 50 mv ?2 ?(0.05 x vrsm) to +2 + (0.05 x vrsm) mv notes: 1. vrsm is the maximum voltage drop across the current sense resistor. 2. analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. there is no reliability concern on digital inputs as long as vind does not exceed these limits. 3. vind is limited to vcc33a + 0.2 to allow reaching 10 mhz input frequency. 4. an averaging of 1,024 samples (lpf setting in analog system builder) is required and the maximum capacitance allowed across the at pins is 500 pf. 5. the temperature offset is a fixed positive value. 6. the high current mode has a maximum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 7. when using smartgen analog system builder, calibip is required to obtain 0 offset. for further details on calibip, refer to the "temperature, voltage, and current calibration in fusion fpgas" chapter of the fusion fpga fabric user?s guide.
fusion family of mixed signal fpgas revision 4 2-121 temperature monitor using analog pad at external temperature monitor (external diode 2n3904, t j = 25c) 4 resolution 8-bit adc 4 c 10-bit adc 1 c 12-bit adc 0.25 c systematic offset 5 afs090 uncalibrated 7 5c afs090, afs250, calibrated 7 0c afs250, afs600, afs1500, uncalibrated 7 11 c afs600, afs1500, calibrated 7 0c accuracy 3 5 c external sensor source current high level, tmstbx = 0 10 a low level, tmstbx = 1 100 a max capacitance on at pad 1.3 nf internal temperature monitor resolution 8-bit adc 4 c 10-bit adc 1 c 12-bit adc 0.25 c systematic offset 5 afs090 uncalibrated 7 5c afs090, afs250, calibrated 7 0c afs250, afs600, afs1500 uncalibrated 7 11 c afs600, afs1500 calibrated 7 0c accuracy 3 5 c t tmshi strobe high time 10 105 s t tmslo strobe low time 5 s t tmsset settling time 5 s table 2-49 ? analog channel specifications (continued) commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: vcc33a = 3.3 v, vcc = 1.5 v parameter description condition min. typ. max. units notes: 1. vrsm is the maximum voltage drop across the current sense resistor. 2. analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. there is no reliability concern on digital inputs as long as vind does not exceed these limits. 3. vind is limited to vcc33a + 0.2 to allow reaching 10 mhz input frequency. 4. an averaging of 1,024 samples (lpf setting in analog system builder) is required and the maximum capacitance allowed across the at pins is 500 pf. 5. the temperature offset is a fixed positive value. 6. the high current mode has a maximum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 7. when using smartgen analog system builder, calibip is required to obtain 0 offset. for further details on calibip, refer to the "temperature, voltage, and current calibration in fusion fpgas" chapter of the fusion fpga fabric user?s guide.
device architecture 2-122 revision 4 digital input using analog pads av, ac and at vind 2,3 input voltage refer to table 3-2 on page 3-3 vhysdin hysteresis 0.3 v vihdin input high 1.2 v vildin input low 0.9 v vmpwdin minimum pulse with 50 ns f din maximum frequency 10 mhz istbdin input leakage current 2 a idyndin dynamic current 20 a t indin input delay 10 ns gate driver output using analog pad ag vg voltage range refer to table 3-2 on page 3-3 ig output current drive high current mode 6 at 1.0 v 20 ma low current mode: 1 a 0.8 1.0 1.3 a low current mode: 3 a 2.0 2.7 3.3 a low current mode: 10 a 7.4 9.0 11.5 a low current mode: 30 a 21.0 27.0 32.0 a ioffg maximum off current 100 na f g maximum switching ra te high current mode 6 at 1.0 v, 1 k ? resistive load 1.3 mhz low current mode: 1 a, 3 m ? resistive load 3khz low current mode: 3 a, 1 m ? resistive load 7khz low current mode: 10 a, 300 k ? resistive load 25 khz low current mode: 30 a, 105 k ? resistive load 78 khz table 2-49 ? analog channel specifications (continued) commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: vcc33a = 3.3 v, vcc = 1.5 v parameter description condition min. typ. max. units notes: 1. vrsm is the maximum voltage drop across the current sense resistor. 2. analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. there is no reliability concern on digital inputs as long as vind does not exceed these limits. 3. vind is limited to vcc33a + 0.2 to allow reaching 10 mhz input frequency. 4. an averaging of 1,024 samples (lpf setting in analog system builder) is required and the maximum capacitance allowed across the at pins is 500 pf. 5. the temperature offset is a fixed positive value. 6. the high current mode has a maximum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 7. when using smartgen analog system builder, calibip is required to obtain 0 offset. for further details on calibip, refer to the "temperature, voltage, and current calibration in fusion fpgas" chapter of the fusion fpga fabric user?s guide.
fusion family of mixed signal fpgas revision 4 2-123 table 2-50 ? adc characteristics in direct input mode commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: vcc33a = 3.3 v, vcc = 1.5 v parameter description condition min. typ. max. units direct input using analog pad av, ac, at vinadc input voltage (direct input) refer to table 3-2 on page 3-3 cinadc input capacitance channel not selected 7 pf channel selected but not sampling 8pf channel selected and sampling 18 pf zinadc input impedance 8-bit mode 2 k ? 10-bit mode 2 k ? 12-bit mode 2 k ? analog reference voltage varef varef accuracy t j = 25c 2.537 2.56 2.583 v temperature drift of internal reference 65 ppm / c external reference 2.527 vcc33a + 0.05 v adc accuracy (using external reference) 1,2 dc accuracy tue total unadjusted error 8-bit mode 0.29 lsb 10-bit mode 0.72 lsb 12-bit mode 1.8 lsb inl integral non-linearity 8-bit mode 0.20 0.25 lsb 10-bit mode 0.32 0.43 lsb 12-bit mode 1.71 1.80 lsb dnl differential non-linearity (no missing code) 8-bit mode 0.20 0.24 lsb 10-bit mode 0.60 0.65 lsb 12-bit mode 2.40 2.48 lsb offset error 8-bit mode 0.01 0.17 lsb 10-bit mode 0.05 0.20 lsb 12-bit mode 0.20 0.40 lsb gain error 8-bit mode 0.0004 0.003 lsb 10-bit mode 0.002 0.011 lsb 12-bit mode 0.007 0.044 lsb gain error (with internal reference) all modes 2 % fsr notes: 1. accuracy of the external reference is 2.56 v 4.6 mv. 2. data is based on characterization. 3. the sample rate is time-shared among active analog inputs.
device architecture 2-124 revision 4 dynamic performance snr signal-to-noise ratio 8-bit mode 48.0 49.5 db 10-bit mode 58.0 60.0 db 12-bit mode 62.9 64.5 db sinad signal-to-noise distortion 8-bit mode 47.6 49.5 db 10-bit mode 57.4 59.8 db 12-bit mode 62.0 64.2 db thd total harmonic distortion 8-bit mode ?74.4 ?63.0 dbc 10-bit mode ?78.3 ?63.0 dbc 12-bit mode ?77.9 ?64.4 dbc enob effective number of bits 8-bit mode 7.6 7.9 bits 10-bit mode 9.5 9.6 bits 12-bit mode 10.0 10.4 bits conversion rate conversion time 8-bit mode 1.7 s 10-bit mode 1.8 s 12-bit mode 2 s sample rate 8-bit mode 600 ksps 10-bit mode 550 ksps 12-bit mode 500 ksps table 2-50 ? adc characteristics in direct input mode (continued) commercial temperature range conditions, t j = 85c (unless noted otherwise), typical: vcc33a = 3.3 v, vcc = 1.5 v parameter description condition min. typ. max. units notes: 1. accuracy of the external reference is 2.56 v 4.6 mv. 2. data is based on characterization. 3. the sample rate is time-shared among active analog inputs.
fusion family of mixed signal fpgas revision 4 2-125 table 2-51 ? uncalibrated analog channel accuracy* worst-case industrial conditions, t j = 85c total channel error (lsb) channel input offset error (lsb) channel input offset error (mv) channel gain error (%fsr) analog pad prescaler range (v) neg. max. med. pos. max. neg max med. pos. max. neg. max. med. pos. max. min. typ. max. positive range adc in 10-bit mode av, ac 16 ?22 ?2 12 ?11 ?2 14 ?169 ?32 224 3 0 ?3 8 ?40 ?5 17 ?11 ?5 21 ?87 ?40 166 2 0 ?4 4 ?45 ?9 24 ?16 ?11 36 ?63 ?43 144 2 0 ?4 2 ?70 ?19 33 ?33 ?20 66 ?66 ?39 131 2 0 ?4 1 ?25 ?7 5 ?11 ?3 26 ?11 ?3 26 3 ?1 ?3 0.5 ?41 ?12 8 ?12 ?7 38 ?6 ?4 19 3 ?1 ?3 0.25 ?53 ?14 19 ?20 ?14 40 ?5 ?3 10 5 0 ?4 0.125 ?89 ?29 24 ?40 ?28 88 ?5 ?4 11 7 0 ?5 at 16 ?3 9 15 ?4 0 4 ?64 5 64 1 0 ?1 4 ?10 2 15 ?11 ?2 11 ?44 ?8 44 1 0 ?1 negative range adc in 10-bit mode av, ac 16 ?35 ?10 9 ?24 ?6 9 ?383 ?96 148 5 ?1 ?6 8 ?65 ?19 12 ?34 ?12 9 ?268 ?99 75 5 ?1 ?5 4 ?86 ?28 21 ?64 ?24 19 ?254 ?96 76 5 ?1 ?6 2 ?136 ?53 37 ?115 ?42 39 ?230 ?83 78 6 ?2 ?7 1 ?98 ?35 8 ?39 ?8 15 ?39 ?8 15 10 ?3 ?10 0.5 ?121 ?46 7 ?54 ?14 18 ?27 ?7 9 10 ?4 ?11 0.25 ?149 ?49 19 ?72 ?16 40 ?18 ?4 10 14 ?4 ?12 0.125 ?188 ?67 38 ?112 ?27 56 ?14 ?3 7 16 ?5 ?14 note: *channel accuracy includes prescaler and adc accuracies. for 12-bit mode, multiply the lsb count by 4. for 8-bit mode, divide the lsb count by 4. gain remains the same.
device architecture 2-126 revision 4 table 2-52 ? calibrated analog channel accuracy 1,2,3 worst-case industrial conditions, t j = 85c condition total channel error (lsb) analog pad prescaler range (v) input voltage 4 (v) negative max. median positive max. positive range adc in 10-bit mode av, ac 16 0.300 to 12.0 ?6 1 6 8 0.250 to 8.00 ?6 0 6 4 0.200 to 4.00 ?7 ?1 7 2 0.150 to 2.00 ?7 0 7 1 0.050 to 1.00 ?6 ?1 6 at 16 0.300 to 16.0 ?5 0 5 4 0.100 to 4.00 ?7 ?1 7 negative range adc in 10-bit mode av, ac 16 ?0.400 to ?10.5 ?7 1 9 8 ?0.350 to ?8.00 ?7 ?1 7 4 ?0.300 to ?4.00 ?7 ?2 9 2 ?0.250 to ?2.00 ?7 ?2 7 1 ?0.050 to ?1.00 ?16 ?1 20 notes: 1. channel accuracy includes prescaler and adc accuracies. for 12-bit mode, multiply the lsb count by 4. for 8-bit mode, divide the lsb count by 4. overall accuracy remains the same. 2. requires enabling analog calibration using smartgen anal og system builder. for further details, refer to the "temperature, voltage, and current calibr ation in fusion fpgas" chapter of the fusion fpga fabric user?s guide . 3. calibrated with two-point calibration methodology, using 20% and 80% full-scale points. 4. the lower limit of the input voltage is determined by the prescaler input offset.
fusion family of mixed signal fpgas revision 4 2-127 examples calculating accuracy for an uncalibrated analog channel formula for a given prescaler range, eq 30 gives the output voltage. output voltage = (channel output offset in v) + (input voltage x channel gain) eq 30 where channel output offset in v = channel input of fset in lsbs x equivalent voltage per lsb channel gain factor = 1+ (% channel gain / 100) example input voltage = 5 v chosen prescaler range = 8 v range refer to table 2-51 on page 2-125 . max. output voltage = (max positive input offs et) + (input voltage x max positive channel gain) max. positive input offset = (21 lsb) x (8 mv per lsb in 10-bit mode) max. positive input offset = 166 mv max. positive gain error = +3% max. positive channel gain = 1 + (+3% / 100) max. positive channel gain = 1.03 max. output voltage = (166 mv) + (5 v x 1.03) max. output voltage = 5.316 v table 2-53 ? analog channel accuracy: monitoring standard positive voltages typical conditions, t a = 25c input voltage (v) calibrated typical error per positive prescaler setting 1 (%fsr) direct adc 2,3 (%fsr) 16 v (at) 16 v (12 v) (av/ac) 8 v (av/ac) 4 v (at) 4 v (av/ac) 2 v (av/ac) 1 v (av/ac) varef = 2.56 v 15 1 14 1 12 1 1 5221 3.3 2 2 1 1 1 2.5 3 2 1 1 1 1 1.8 4 4 1 1 1 1 1 1.5 5 5 2 2 2 1 1 1.2 7 6 2 2 2 1 1 0.9 9 9 4 3 3 1 1 1 notes: 1. requires enabling analog calibration using smartgen anal og system builder. for further details, refer to the "temperature, voltage, and current calibr ation in fusion fpgas" chapter of the fusion fpga fabric user?s guide . 2. direct adc mode using an external varef of 2.56v4.6mv, without analog calibration macro. 3. for input greater than 2.56 v, the adc output will sa turate. a higher varef or prescaler usage is recommended.
device architecture 2-128 revision 4 similarly, min. output voltage = (max. negative input offset) + (input voltage x max. negative channel gain) = (?88 mv) + (5 v x 0.96) = 4.712 v calculating accuracy for a calibrated analog channel formula for a given prescaler range, eq 31 gives the output voltage. output voltage = channel error in v + input voltage eq 31 where channel error in v = total channel error in lsbs x equivalent voltage per lsb example input voltage = 5 v chosen prescaler range = 8 v range refer to table 2-52 on page 2-126 . max. output voltage = max. positive channel error in v + input voltage max. positive channel error in v = (6 lsb) (8 mv per lsb in 10-bit mode) = 48 mv max. output voltage = 48 mv + 5 v = 5.048 v similarly, min. output voltage = max. negative channel error in v + input voltage = (?48 mv) + 5 v = 4.952 v calculating lsbs from a given error budget formula for a given prescaler range, lsb count = (input voltage required % error) / (equivalent voltage per lsb) example input voltage = 3.3 v required error margin= 1% refer to table 2-52 on page 2-126 . equivalent voltage per lsb = 16 mv for a 16v prescaler, with adc in 10-bit mode lsb count = (5.0 v 1%) / (0.016) lsb count = 3.125 equivalent voltage per lsb = 8 mv for an 8 v prescaler, with adc in 10-bit mode lsb count = (5.0 v 1%) / (0.008) lsb count = 6.25 the 8 v prescaler satisfies the calculated lsb count accuracy requirement (see ta b l e 2 - 5 2 o n page 2-126 ).
fusion family of mixed signal fpgas revision 4 2-129 analog configuration mux the acm is the interface between t he fpga, the analog block configurations, and the real-time counter. microsemi libero soc will generat e ip that will load and configure the analog block via the acm. however, users are not limited to using the libero so c ip. this section provides a detailed description of the acm's register map, truth tables for proper conf iguration of the analog block and rtc, as well as timing waveforms so us ers can access and control the acm directly from their designs. the analog block contains four 8-bit latches per analog quad that are initialized through the acm. these latches act as configuration bits for analog quads. the acm block runs from the core voltage supply (1.5 v). access to the acm is achieved via 8-bit address and da ta busses with enables. the pin list is provided in table 2-36 on page 2-81 . the acm clock speed is limited to a maximum of 10 mhz, more than sufficient to handle the low-bandwidth requirements of configur ing the analog block and the rtc (sub-block of the analog block). table 2-54 decodes the acm address space and maps it to the corresponding analog quad and configuration byte for that quad. table 2-54 ? acm address decode table for analog quad acmaddr [7:0] in decimal name description associated peripheral 0 ? ? analog quad 1 aq0 byte 0 analog quad 2 aq0 byte 1 analog quad 3 aq0 byte 2 analog quad 4 aq0 byte 3 analog quad 5 aq1 byte 0 analog quad . . . . . . . . . analog quad 36 aq8 byte 3 analog quad 37 aq9 byte 0 analog quad 38 aq9 byte 1 analog quad 39 aq9 byte 2 analog quad 40 aq9 byte 3 analog quad 41 undefined analog quad . . . . . . undefined analog quad 63 undefined rtc 64 counter0 counter bits 7:0 rtc 65 counter1 counter bits 15:8 rtc 66 counter2 counter bits 23:16 rtc 67 counter3 counter bits 31:24 rtc 68 counter4 counter bits 39:32 rtc 72 matchreg0 match register bits 7:0 rtc 73 matchreg1 match register bits 15:8 rtc
device architecture 2-130 revision 4 acm characteristics 1 74 matchreg2 match register bits 23:16 rtc 75 matchreg3 match register bits 31:24 rtc 76 matchreg4 match register bits 39:32 rtc 80 matchbits0 individual match bits 7:0 rtc 81 matchbits1 individual match bits 15:8 rtc 82 matchbits2 individual match bits 23:16 rtc 83 matchbits3 individual match bits 31:24 rtc 84 matchbits4 individual match bits 39:32 rtc 88 ctrl_stat control (write) / status (read) register bits 7:0 rtc note: acmaddr bytes 1 to 40 pertain to the analog quads; bytes 64 to 89 pertain to the rtc. 1. when addressing the rtc addresses (i.e., acmaddr 64 to 89), there is no timing generator, and the rc_osc, byte_en, and aq_wen signals have no impact. table 2-54 ? acm address decode table for analog quad (continued) acmaddr [7:0] in decimal name description associated peripheral figure 2-97 ? acm write waveform figure 2-98 ? acm read waveform d1 a1 t sueacm t heacm t sudacm t hdacm t suaacm t haacm a0 d0 acmclk acmwen acmwdata acmaddress a0 a1 rd0 rd1 t mpwclkacm t clkqacm acmclk acmaddress acmrdata
fusion family of mixed signal fpgas revision 4 2-131 timing characteristics table 2-55 ? analog configuration multiplexer (acm) timing commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t clkqacm clock-to-q of the acm 19.73 22.48 26.42 ns t sudacm data setup time for the acm 4.39 5.00 5.88 ns t hdacm data hold time for the acm 0.00 0.00 0.00 ns t suaacm address setup time for the acm 4.73 5.38 6.33 ns t haacm address hold time for the acm 0.00 0.00 0.00 ns t sueacm enable setup time for the acm 3.93 4.48 5.27 ns t heacm enable hold time for the acm 0.00 0.00 0.00 ns t mpwaracm asynchronous reset minimum pulse width for the acm 10.00 10.00 10.00 ns t remaracm asynchronous reset re moval time for the ac m 12.98 14.79 17.38 ns t recaracm asynchronous reset recovery time for the acm 12.98 14.79 17.38 ns t mpwclkacm clock minimum pulse width for the acm 45.00 45.00 45.00 ns t fmaxclkacm lock maximum frequency for the acm 10.00 10.00 10.00 mhz
device architecture 2-132 revision 4 analog quad acm description table 2-56 maps out the acm space associated with co nfiguration of the analog quads within the analog block. table 2-56 shows the byte assignment within each quad and the function of each bit within each byte. subsequent tables will explain each bit setting and how it corresponds to a particular configuration. after 3.3 v and 1.5 v are applied to fusion, analog quad c onfiguration registers are loaded with default settings until the initialization and configuration state machine changes them to user- defined settings. table 2-56 ? analog quad acm byte assignment byte bit signal (bx) fu nction default setting byte 0 (av) 0 b0[0] scaling factor control ? prescaler highest voltage range 1 b0[1] 2 b0[2] 3 b0[3] analog mux select prescaler 4 b0[4] current monitor switch off 5 b0[5] direct analog input switch off 6 b0[6] selects v-pad polarity positive 7 b0[7] prescaler op amp mode power-down byte 1 (ac) 0 b1[0] scaling factor control ? prescaler highest voltage range 1 b1[1] 2 b1[2] 3 b1[3] analog mux select prescaler 4 b1[4] 5 b1[5] direct analog input switch off 6 b1[6] selects c-pad polarity positive 7 b1[7] prescaler op amp mode power-down byte 2 (ag) 0 b2[0] internal chip temperature monitor * off 1 b2[1] spare ? 2 b2[2] current drive control lowest current 3 b2[3] 4 b2[4] spare ? 5 b2[5] spare ? 6 b2[6] selects g-pad polarity positive 7 b2[7] selects low/high drive low drive byte 3 (at) 0 b3[0] scaling factor control ? prescaler highest voltage range 1 b3[1] 2 b3[2] 3 b3[3] analog mux select prescaler 4 b3[4] 5 b3[5] direct analog input switch off 6 b3[6] ? ? 7 b3[7] prescaler op amp mode power-down note: *for the internal temperature monitor to function , bit 0 of byte 2 for all 10 quads must be set.
fusion family of mixed signal fpgas revision 4 2-133 table 2-57 details the settings available to control the pr escaler values of the av, ac, and at pins. note that the at pin has a reduced numbe r of available prescaler values. table 2-58 details the settings available to control the mux within each of the av, ac, and at circuits. this mux determines whether the signal routed to the adc is the direct analog input, prescaled signal, or output of either the current monitor block or the temperature monitor block. table 2-59 details the settings available to control the direct analog input switch for the av, ac, and at pins. table 2-60 details the settings available to control the polarity of the signals coming to the av, ac, and at pins. note that the only valid setting for the at pin is logic 0 to support positive voltages. table 2-57 ? prescaler control truth table?av (x = 0), ac (x = 1), and at (x = 3) control lines bx[2:0] scaling factor, pad to adc input lsb for an 8-bit conversion 1 (mv) lsb for a 10-bit conversion 1 (mv) lsb for a 12-bit conversion 1 (mv) full-scale voltage in 10-bit mode 2 range name 000 3 0.15625 64 16 4 16.368 v 16 v 001 0.3125 32 8 2 8.184 v 8 v 010 3 0.625 16 4 1 4.092 v 4 v 011 1.25 8 2 0.5 2.046 v 2 v 100 2.5 4 1 0.25 1.023 v 1 v 101 5.0 2 0.5 0.125 0.5115 v 0.5 v 110 10.0 1 0.25 0.0625 0.25575 v 0.25 v 111 20.0 0.5 0.125 0. 03125 0.127875 v 0.125 v notes: 1. lsb voltage equivalences assume varef = 2.56 v. 2. full scale voltage for n-bit mode: ((2^n) - 1) x (lsb for a n-bit conversion) 3. these are the only valid ranges for the temperature monitor block prescaler. table 2-58 ? analog multiplexer truth table?av (x = 0), ac (x = 1), and at (x = 3) control lines bx[4] control lines bx[3] adc connected to 0 0 prescaler 0 1 direct input 1 0 current amplifier temperature monitor 1 1 not valid table 2-59 ? direct analog input switch control truth table?av (x = 0), ac (x = 1), and at (x = 3) control lines bx[5] direct input switch 0 off 1 on table 2-60 ? voltage polarity control truth table?av (x = 0), ac (x = 1), and at (x = 3)* control lines bx[6] input signal polarity 0 positive 1 negative note: *the b3[6] signal for the at pad should be k ept at logic 0 to accept only positive voltages.
device architecture 2-134 revision 4 table 2-61 details the settings available to either power down or enable the prescaler associated with the analog inputs av, ac, and at. table 2-62 details the settings available to enable the current monitor block associated with the ac pin. table 2-63 details the settings available to configure the drive strength of the gat e drive when not in high- drive mode. table 2-64 details the settings available to set the polar ity of the gate driver (either p-channel- or n-channel-type devices). table 2-65 details the settings available to turn on the ga te driver and set whether high-drive mode is on or off. table 2-66 details the settings available to turn on and off the chip internal temperature monitor. note: for the internal temperature moni tor to function, bit 0 of byte 2 for all 10 quads must be set. table 2-61 ? prescaler op amp power-down truth table? av (x = 0), ac (x = 1), and at (x = 3) control lines bx[7] prescaler op amp 0 power-down 1 operational table 2-62 ? current monitor input switch control truth table?av (x = 0) control lines b0[4] current monitor input switch 0 off 1 on table 2-63 ? low-drive gate driver current truth table (ag) control lines b2[3] control lines b2[2] current (a) 0 0 1 0 1 3 1 0 10 1 1 30 table 2-64 ? gate driver polarity truth table (ag) control lines b2[6] gate driver polarity 0 positive 1 negative table 2-65 ? gate driver control truth table (ag) control lines b2[7] gdon gate driver 0 0 off 0 1 low drive on 1 0 off 1 1 high drive on table 2-66 ? internal temperature monitor control truth table control lines b2[0] pdtmb chip internal temperature monitor 00off 11on
fusion family of mixed signal fpgas revision 4 2-135 user i/os introduction fusion devices feature a flexible i/o structure, s upporting a range of mixed voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v) through a bank-selectable voltage. table 2-68 , ta b l e 2 - 6 9 , ta b l e 2 - 7 0 , and table 2-71 on page 2-138 show the voltages and the compatible i/o stand ards. i/os provide programmable slew rates, drive strengths, weak pull-up, and weak pull-down circuits. 3.3 v pc i and 3.3 v pci-x are 5 v?tolerant. see the "5 v input tolerance" section on page 2-147 for possible implementations of 5 v tolerance. all i/os are in a known state during power-up, and any power-up sequence is allowed without current impact. refer to the "i/o power-up and supply voltage thresh olds for power-on reset (commercial and industrial)" section on page 3-5 for more information. in low power standby or sleep mode (vcc is off, vcc33a is on, vcci is on) or when the resource is not used, digital inputs are tristated, digital outputs are tristated, and digital bibufs (input/output) are tristated. i/o tile the fusion i/o tile provides a flexible, programma ble structure for implementing a large number of i/o standards. in addition, the registers available in the i/o tile in selected i/o banks can be used to support high-performance register inputs and output s, with register enable if desired ( figure 2-99 on page 2-136 ). the registers can also be used to s upport the jesd-79c ddr standard within the i/o structure (see the "double data rate (ddr) support" section on page 2-142 for more information). as depicted in figure 2-100 on page 2-141 , all i/o registers share one clr port. the output register and output enable register share one clk port. refer to the "i/o registers" section on page 2-141 for more information. i/o banks and i/o st andards compatibility the digital i/os are grouped into i/o voltage banks. there are three digital i/o banks on the afs090 and afs250 devices and four digital i/o banks on the afs600 and afs1500 devices. figure 2-113 on page 2-161 and figure 2-114 on page 2-162 show the bank configuration by device. the north side of the i/o in the afs600 and afs1500 devices comprise s two banks of pro i/os. the pro i/os support a wide number of voltage-referenced i/o standards in addition to the multitude of single-ended and differential i/o standards common throughout all microsemi digital i/os. each i/o voltage bank has dedicated i/o supply and ground voltages (vcci/g ndq for input buffers and vcci/gnd for output buffers). because of these dedica ted supplies, only i/os with compatible standards can be assigned to the same i/o voltage bank. table 2-69 and table 2-70 on page 2-137 show the required voltage compatibility values for each of these voltages. for more information about i/o and global assignments to i/o banks, refer to the specific pin table of the device in the "package pin assignments" on page 4-1 and the "user i/o naming convention" section on page 2-161 . each pro i/o bank is divided into minibanks. any us er i/o in a vref minibank (a minibank is the region of scope of a vref pin) can be configured as a vref pin ( figure 2-99 on page 2-136 ). only one vref pin is needed to control the entire vref minibank. the location and scope of the vref minibanks can be determined by the i/o name. for details, see the "user i/o naming convention" section on page 2-161 . table 2-70 on page 2-137 shows the i/o standards supported by fusion devices and the corresponding voltage levels. i/o standards are compatible if the following are true: ? their vcci values are identical. ? if both of the standards need a vref, their vref values must be identical (pro i/o only).
device architecture 2-136 revision 4 figure 2-99 ? fusion pro i/o bank detail showing vref minibanks (north side ofafs600 and afs1500) table 2-67 ? i/o standards supported by bank type i/o bank single-ended i/o standards differential i/o standards voltage-referenced hot- swap standard i/o lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v ?? yes advanced i/o lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v, 3.3 v pci / 3.3 v pci- x lvpecl and lvds ?? pro i/o lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v, 3.3 v pci / 3.3 v pci- x lvpecl and lvds gtl+ 2.5 v / 3.3 v, gtl 2.5 v / 3.3 v, hstl class i and ii, sstl2 class i and ii, sstl3 class i and ii yes bank 1 bank 0 i/o i/o gnd i/o i/o i/o i/o gnd i/o i/o i/o pad if needed, the vref for a given minibank can be provided by any i/o within the minibank. ccc ccc ccc up to five vref minibanks within an i/o bank vref signal scope is between 8 and 18 i/os. common vref signal for all i/os in vref minibanks vcci vcc vcci vcc
fusion family of mixed signal fpgas revision 4 2-137 table 2-68 ? i/o bank support by device i/o bank afs090 afs250 afs600 afs1500 standard i/o n n ? ? advanced i/o e, w e, w e, w e, w pro i/o ? ? n n analog quadssss note: e = east side of the device w = west side of the device n = north side of the device s = south side of the device table 2-69 ? fusion vcci voltages and compatible standards vcci (typical) compatible standards 3.3 v lvttl/lvcmos 3.3, pci 3. 3, sstl3 (class i and ii),* gtl+ 3.3, gtl 3.3,* lvpecl 2.5 v lvcmos 2.5, lvcmos 2.5/5.0, sstl2 (class i and ii),* gt l+ 2.5,* gtl 2.5,* lvds, blvds, m- lvds 1.8 v lvcmos 1.8 1.5 v lvcmos 1.5, hstl (cla ss i),* hstl (class ii)* note: *i/o standard supported by pro i/o banks. table 2-70 ? fusion vref voltages and compatible standards* vref (typical) compatible standards 1.5 v sstl3 (class i and ii) 1.25 v sstl2 (class i and ii) 1.0 v gtl+ 2.5, gtl+ 3.3 0.8 v gtl 2.5, gtl 3.3 0.75 v hstl (class i), hstl (class ii) note: *i/o standards supported by pro i/o banks.
device architecture 2-138 revision 4 table 2-71 ? fusion standard and advanced i/o features i/o bank voltage (typical) minibank voltage (typical) lvttl/lvcmos 3.3 v lvcmos 2.5 v lvcmos 1.8 v lvcmos 1.5 v 3.3 v pci / pci-x gtl + (3.3 v) gtl + (2.5 v) gtl (3.3 v) gtl (2.5 v) hstl class i and ii (1.5 v) sstl2 class i and ii (2.5 v) sstl3 class i and ii (3.3 v) lvds (2.5 v 5%) lvpecl (3.3 v) 3.3 v ? 0.80 v 1.00 v 1.50 v 2.5 v ? 0.80 v 1.00 v 1.25 v 1.8 v ? 1.5 v ? 0.75 v note: white box: allowable i/o standard combinations gray box: illegal i/o standard combinations
fusion family of mixed signal fpgas revision 4 2-139 features supported on pro i/os table 2-72 lists all features supported by transmitter/re ceiver for single-ended and differential i/os. table 2-72 ? fusion pro i/o features feature description single-ended and voltage- referenced transmitter features ? hot insertion in every mode except pci or 5 v input tolerant (these modes use clamp diodes and do not allow hot insertion) ? activation of hot insertion (disabling the clamp diode) is selectable by i/os. ? weak pull-up and pull-down ? two slew rates ? skew between output buffer enable/disable time: 2 ns delay (rising edge) and 0 ns delay (falling edge); see "selectable skew between output buffer enable/disable time" on page 2-152 for more information ? five drive strengths ? 5 v?tolerant receiver ( "5 v input tolerance" section on page 2-147 ) ? lvttl/lvcmos 3.3 v outputs compatible with 5 v ttl inputs ( "5 v output tolerance" section on page 2-151 ) ? high performance ( table 2-76 on page 2-146 ) single-ended receiver features ? schmitt trigger option ? esd protection ? programmable delay: 0 ns if bypass ed, 0.625 ns with '000' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25c, 1.5 v) ? high performance ( table 2-76 on page 2-146 ) ? separate ground planes, gnd/gndq, fo r input buffers only to avoid output- induced noise in the input circuitry voltage-referenced differential receiver features ? programmable delay: 0 ns if bypass ed, 0.625 ns with '000' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25c, 1.5 v) ? high performance ( table 2-76 on page 2-146 ) ? separate ground planes, gnd/gndq, fo r input buffers only to avoid output- induced noise in the input circuitry cmos-style lvds, blvds, m-lvds, or lvpecl transmitter ? two i/os and external resistors ar e used to provide a cmos-style lvds, blvds, m-lvds, or lvpecl transmitter solution. ? activation of hot insertion (disabling the clamp diode) is selectable by i/os. ? weak pull-up and pull-down ? fast slew rate lvds/lvpecl differential receiver features ? esd protection ? high performance ( table 2-76 on page 2-146 ) ? programmable delay: 0.625 ns with '000 ' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25c, 1.5 v) ? separate input buffer ground and power planes to avoid output-induced noise in the input circuitry
device architecture 2-140 revision 4 table 2-73 ? maximum i/o frequency for single-ended, vo ltage-referenced, and differential i/os; all i/o bank types (maximum drive st rength and high slew selected) specification performance up to lvttl/lvcmos 3.3 v 200 mhz lvcmos 2.5 v 250 mhz lvcmos 1.8 v 200 mhz lvcmos 1.5 v 130 mhz pci 200 mhz pci-x 200 mhz hstl-i 300 mhz hstl-ii 300 mhz sstl2-i 300 mhz sstl2-ii 300 mhz sstl3-i 300 mhz sstl3-ii 300 mhz gtl+ 3.3 v 300 mhz gtl+ 2.5 v 300 mhz gtl 3.3 v 300 mhz gtl 2.5 v 300 mhz lvds 350 mhz lvpecl 300 mhz
fusion family of mixed signal fpgas revision 4 2-141 i/o registers each i/o module contains several input, output, and enable registers. refer to figure 2-100 for a simplified representation of the i/o block. the number of input registers is select ed by a set of switches (not shown in figure 2-100 ) between registers to implement single or differential data transmission to and from the fpga core. the designer software sets these switches for the user. a common clr/pre signal is employed by all i/o registers when i/o register combining is used. input register 2 does not have a clr/pre pin, as this register is used for ddr implementation. the i/o register combining must satisfy some rules. note: fusion i/os have registers to support ddr functionality (see the "double data rate (ddr) support" section on page 2-142 for more information). figure 2-100 ? i/o block logical representation input reg e = enable pin a y pad 1 2 3 4 5 6 oce ice ice input reg input reg clr/pre clr/pre clr/pre clr/pre clr/pre pull-up/down resistor control signal drive strength and slew-rate control output reg output reg to fpga core from fpga core output enable reg oce i/o / clr or i/o / pre / oce i/o / q0 i/o / q1 i/o / iclk i/o / d0 i/o / d1 / ice i/o / oclk i/o / oe
device architecture 2-142 revision 4 double data rate (ddr) support fusion pro i/os support 350 mhz ddr inputs and outpu ts. in ddr mode, new data is present on every transition of the clock signal. clock and data lines have identical bandwidths and signal integrity requirements, making it very efficien t for implementing very high-speed systems. ddr interfaces can be implemented using hstl, sst l, lvds, and lvpecl i/o standards. in addition, high-speed ddr interfaces can be implemented using lvds i/o. input support for ddr the basic structure to support a ddr input is shown in figure 2-101 . three input registers are used to capture incoming data, which is presented to the core on each rising edge of the i/o register clock. each i/o tile on fusion devices supports ddr inputs. output support for ddr the basic ddr output structure is shown in figure 2-102 on page 2-143 . new data is presented to the output every half clock cycle. note: ddr macros and i/o registers do not requir e additional routing. the combiner automatically recognizes the ddr macro and pus hes its registers to the i/o register area at the edge of the chip. the routing delay from the i/o regist ers to the i/o buffers is already taken into account in the ddr macro. refer to the application note using ddr for fusion devices for more information. figure 2-101 ? ddr input register supp ort in fusion devices input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
fusion family of mixed signal fpgas revision 4 2-143 figure 2-102 ? ddr output support in fusion devices data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out ff1 0 1 a b d e c c b outbuf data_r (from core)
device architecture 2-144 revision 4 hot-swap support hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered-up system. th e levels of hot-swap supp ort and examples of re lated applications are described in ta b l e 2 - 7 4 . the i/os also need to be configured in hot insertion mode if hot plugging compliance is required. table 2-74 ? levels of hot-swap support hot swapping level description power applied to device bus state card ground connection device circuitry connected to bus pins example of application with cards that contain fusion devices compliance of fusion devices 1 cold-swap no ? ? ? system and card with microsemi fpga chip are powered down, then card gets plugged into system, then power supplies are turned on for system but not for fpga on card. compliant i/os can but do not have to be set to hot insertion mode. 2 hot-swap while reset yes held in reset state must be made and maintained for 1 ms before, during, and after insertion/ removal ? in pci hot plug specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. compliant i/os can but do not have to be set to hot insertion mode. 3 hot-swap while bus idle yes held idle (no ongoing i/o processes during insertion/re moval) same as level 2 must remain glitch-free during power-up or power-down board bus shared with card bus is "frozen," and there is no toggling activity on bus. it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. compliant with cards with two levels of staging. i/os have to be set to hot insertion mode. 4 hot-swap on an active bus yes bus may have active i/o processes ongoing, but device being inserted or removed must be idle. same as level 2 same as level 3 there is activity on the system bus, and it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. compliant with cards with two levels of staging. i/os have to be set to hot insertion mode.
fusion family of mixed signal fpgas revision 4 2-145 for fusion devices requiring level 3 and/or level 4 compliance, the board driv ers connected to fusion i/os need to have 10 k ? (or lower) output drive resistance at hot insertion, and 1 k ? (or lower) output drive resistance at hot removal. th is is the resistance of the transmi tter sending a signal to the fusion i/o, and no additional resistance is needed on th e board. if that cannot be assured, three levels of staging can be used to meet level 3 and/or level 4 compliance. cards with two levels of staging should have the following sequence: 1. grounds 2. powers, i/os, other pins cold-sparing support cold-sparing means that a subsys tem with no power applied (usually a circuit board) is electrically connected to the system that is in operation. this means that all input buffers of the subsystem must present very high input impedance wit h no power applied so as not to disturb the operating portion of the system. pro i/o banks and standard i/o banks fully support cold-sparing. for pro i/o banks, standards such as pci that require i/o clamp diodes, can also achieve cold-sparing compliance, since clamp diodes get disconnect ed internally when the supplies are at 0 v. for advanced i/o banks, since the i/o clamp diode is always active, cold-sparing can be accomplished either by employing a bus switch to isolate the device i/os from the rest of the system or by driving each advanced i/o pin to 0 v. if standard i/o banks are used in applications requi ring cold-sparing, a discharge path from the power supply to ground should be provided. this can be done wi th a discharge resistor or a switched resistor. this is necessary because the standard i/o buffers do not have built-in i/o clamp diodes. if a resistor is chosen, the resi stor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitor is in parallel with the resistor). the rc time constant should ensure full discharge of supplies before cold-sparing function ality is required. the resistor is necessary to ensure that the power pi ns are discharged to ground every time there is an interruption of power to the device. i/o cold-sparing may add additional current if t he pin is configured with either a pull-up or pull down resistor and driven in the opposite di rection. a small static current is induced on each io pin when the pin is driven to a voltage opposite to the weak pull resistor. the current is equal to the voltage drop across the input pin divided by the pull resistor. please refer to table 2-95 on page 2-172 , table 2-96 on page 2-172 , and table 2-97 on page 2-174 for the specific pull resistor value for the corresponding i/o standard. for example, assuming an lvttl 3.3 v input pin is conf igured with a weak pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven low. for an lv ttl 3.3 v, pull-up resistor is ~45 k ? and the resulting current is equal to 3.3 v / 45 k ? = 73 a for the i/o pin. this is true also when a weak pull-down is chosen and the input pin is driven high. avoiding this current can be done by driving the input low when a weak pull-down resistor is used, and driving it high when a weak pull-up resistor is used. in active and static modes, this current draw can occur in the following cases: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers with pull-up, driven low ? bidirectional buffers with pull-down, driven high ? output buffers with pull-up, driven low ? output buffers with pull-down, driven high ? tristate buffers with pull-up, driven low ? tristate buffers with pull-down, driven high
device architecture 2-146 revision 4 electrostatic discharge (esd) protection fusion devices are tested per jedec standard jesd22-a114-b. fusion devices contain clamp diodes at every i/o, global, and power pad. clamp diodes protect all device pads against damage from esd as well as from excessive voltage transients. each i/o has two clamp diodes. one diode has its positive (p) side connected to the pad and its negative (n) side connected to vcci. the second diode has its p side connected to gnd and its n side connected to the pad. during operat ion, these diodes are normally biased in the off state, except when transient voltage is significantly above vcci or below gnd levels. by selecting the appropriate i/o configuratio n, the diode is turned on or off. refer to ta b l e 2 - 7 5 and table 2-76 on page 2-146 for more information about i/o standards and the clamp diode. the second diode is always connected to the pad, regardless of the i/o configuration selected. table 2-75 ? fusion standard and advanced i/o ? hot-swap and 5 v input tolerance capabilities i/o assignment clamp diode hot insertion 5 v input tolerance 1 input buffer output buffer standard i/o advanced i/o standard i/o advanced i/o standard i/o advanced i/o 3.3 v lvttl/lvcmos no yes yes no yes 1 yes 1 enabled/disabled 3.3 v pci, 3.3 v pci-x n/a yes n/a no n/a yes 1 enabled/disabled lvcmos 2.5 v no yes yes no no no enabled/disabled lvcmos 2.5 v / 5.0 v n/a yes n/a no n/a yes 2 enabled/disabled lvcmos 1.8 v no yes yes no no no enabled/disabled lvcmos 1.5 v no yes yes no no no enabled/disabled differential, lvds/blvds/m- lvds/ lvpecl 3 n/a yes n/a no n/a no enabled/disabled notes: 1. can be implemented with an external idt bus sw itch, resistor divider, or zener with resistor. 2. can be implemented with an external resistor and an internal clamp diode. 3. bidirectional lvpecl buffers are not supported. i/os can be configured as either input buffers or output buffers. table 2-76 ? fusion pro i/o ? hot-swap and 5 v input tolerance capabilities i/o assignment clamp diode hot insertion 5 v input tolerance input bu ffer output buffer 3.3 v lvttl/lvcmos no yes yes 1 enabled/disabled 3.3 v pci, 3.3 v pci-x yes no yes 1 enabled/disabled lvcmos 2.5 v 3 no yes no enabled/disabled lvcmos 2.5 v / 5.0 v 3 yes no yes 2 enabled/disabled lvcmos 1.8 v no yes no enabled/disabled lvcmos 1.5 v no yes no enabled/disabled voltage-referenced input buffer no yes no enabled/disabled differential, lvds/blvds/m-lvds/lvpecl 4 no yes no enabled/disabled notes: 1. can be implemented with an external idt bus swit ch, resistor divider, or zener with resistor. 2. can be implemented with an external resistor and an internal clamp diode. 3. in the smartgen, flashrom, flash memory system builder, and analog system builder user's guide , select the lvcmos5 macro for the lvcmos 2.5 v / 5.0 v i/o stan dard or the lvcmos25 macro for the lvcmos 2.5 v i/o standard. 4. bidirectional lvpecl buffers are not supported. i/os c an be configured as either input buffers or output buffers.
fusion family of mixed signal fpgas revision 4 2-147 5 v input tolerance i/os can support 5 v input tolerance when lvttl 3.3 v, lvcmos 3.3 v, lvcmos 2.5 v / 5 v, and lvcmos 2.5 v configurations are used (see table 2-77 on page 2-150 for more details). there are four recommended solutions (see figure 2-103 to figure 2-106 on page 2-149 for details of board and macro setups) to achieve 5 v receiver tolerance. all the solutions meet a common requirement of limiting the voltage at the input to 3.6 v or less. in fact, t he i/o absolute maximum voltage rating is 3.6 v, and any voltage above 3.6 v may cause long-term gate oxide failures. solution 1 the board-level design needs to ensure that the refl ected waveform at the pa d does not exceed the limits provided in table 3-4 on page 3-4 . this is a long-term reliability requirement. this scheme will also work for a 3.3 v pci / pci-x c onfiguration, but the inte rnal diode should not be used for clamping, and the voltage must be limited by the two external resistors, as explained below. relying on the diode clamping would create an exce ssive pad dc voltage of 3.3 v + 0.7 v = 4 v. the following are some examples of possible resistor values (based on a simplified simulation model with no line effects and 10 ? transmitter output resistance, w here rtx_out_high = (vcci ? voh) / ioh, rtx_out_low = vol / iol). example 1 (high speed, high current): rtx_out_high = rtx_out_low = 10 ? r1 = 36 ? (5%), p(r1)min = 0.069 ? r2 = 82 ? (5%), p(r2)min = 0.158 ? imax_tx = 5.5 v / (82 * 0.95 + 36 * 0.95 + 10) = 45.04 ma t rise =t fall = 0.85 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise =t fall = 4 ns at c_pad_load = 50 pf (includes up to 25% safety margin) example 2 (low?medium speed, medium current): rtx_out_high = rtx_out_low = 10 ? r1 = 220 ? (5%), p(r1)min = 0.018 ? r2 = 390 ? (5%), p(r2)min = 0.032 ? imax_tx = 5.5 v / (220 * 0.95 + 390 * 0.95 + 10) = 9.17 ma t rise =t fall = 4 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise =t fall = 20 ns at c_pad_load = 50 pf (includes up to 25% safety margin) other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 v < vin(rx) < 3.6 v when the transmitter sends a logic 1. this range of vin_dc(rx) must be assured for any combination of transmitter supply (5 v 0.5 v), transmitter output resistance, and board resistor tolerances.
device architecture 2-148 revision 4 temporary overshoots are allowed according to table 3-4 on page 3-4 . solution 2 the board-level design must ensure that the refl ected waveform at the pad does not exceed limits provided in table 3-4 on page 3-4 . this is a long-term reliability requirement. this scheme will also work for a 3.3 v pci/pci-x conf iguration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and zener, as shown in figure 2- 104 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. figure 2-103 ? solution 1 figure 2-104 ? solution 2 on-chip off-chip solution 1 5.5 v 3.3 v requires two board resistors, lvcmos 3.3 v i/os fusion i/o input rext1 rext2 solution 2 5.5 v 3.3 v requires one board resistor, one zener 3.3 v diode, lvcmos 3.3 v i/os fusion i/o input rext1 zener 3.3 v on-chip off-chip
fusion family of mixed signal fpgas revision 4 2-149 solution 3 the board-level design must ensure that the refl ected waveform at the pad does not exceed limits provided in table 3-4 on page 3-4 . this is a long-term reliability requirement. this scheme will also work for a 3.3 v pci/pcix conf iguration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in figure 2-105 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. solution 4 figure 2-105 ? solution 3 figure 2-106 ? solution 4 solution 3 requires a bus switch on the board, lvttl/lvcmos 3.3 v i/os. fusion i/o input 3.3 v 5.5 v 5.5 v bus switch idtqs32x23 on-chip off-chip solution 4 2.5 v on-chip clamp diode requires one board resistor. available for lvcmos 2.5 v / 5.0 v. on-chip off-chip 5.5 v 2.5 v fusion i/o input rext1
device architecture 2-150 revision 4 table 2-77 ? comparison table for 5 v?compliant receiver scheme schem e board components speed current limitations 1 two resistors low to high 1 limited by transmitter's drive strength 2 resistor and zener 3.3 v medium limited by transmitter's drive strength 3 bus switch high n/a 4 minimum resistor value 2 r = 47 ? at t j = 70c r = 150 ? at t j = 85c r = 420 ? at t j = 100c medium maximum diode current at 100 % duty cycle, signal constantly at '1' 52.7 ma at t j =70c / 10-year lifetime 16.5 ma at t j = 85c / 10-year lifetime 5.9 ma at t j = 100c / 10-year lifetime for duty cycles other than 100%, the currents can be increased by a factor = 1 / (duty cycle). example: 20% duty cycle at 70c maximum current = (1 / 0.2) * 52.7 ma = 5 * 52.7 ma = 263.5 ma notes: 1. speed and current consumption increase as the board resistance values decrease. 2. resistor values ensure i/o diode long-term reliability.
fusion family of mixed signal fpgas revision 4 2-151 5 v output tolerance fusion i/os must be set to 3.3 v lvttl or 3.3 v lvcmos mode to reliably drive 5 v ttl receivers. it is also critical that there be no external i/o pull-up resi stor to 5 v, since this resistor would pull the i/o pad voltage beyond the 3.6 v absolute maximum va lue and consequently cause damage to the i/o. when set to 3.3 v lvttl or 3.3 v lvcmos mode, fusion i/os can directly drive signals into 5 v ttl receivers. in fact, vol = 0.4 v and voh = 2.4 v in both 3.3 v lvttl and 3.3 v lvcmos modes exceed the vil = 0.8 v and vih = 2 v level requirements of 5 v ttl receivers. therefore, level '1' and level '0' will be recognized correctly by 5 v ttl receivers. simultaneously switching outputs and pcb layout ? simultaneously switching outputs (ssos) can produce signal integrity problems on adjacent signals that are not part of the sso bus. both inductive and capacitive coupling parasitics of bond wires inside packages and of traces on pcbs will transfer noise from sso busses onto signals adjacent to those busses. additionally, ssos can produce ground bounce noise and vcci dip noise. these two noise types are caused by rapidly changing currents through gnd and vcci package pin inductances during switching activities: ? ground bounce noise voltage = l(gnd) * di/dt ? vcci dip noise voltage = l(vcci) * di/dt any group of four or more input pins switching on the same clock edge is considered an sso bus. the shielding should be done both on the board and in side the package unless otherwise described. in-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to sso bus are lvttl/ lvcmos inputs, lvttl/lvcmos outputs, or gtl/sstl/hstl/lvds/lvpecl inputs and outputs. boar d traces in the vicinity of the sso bus have to be adequately shielded from mutual coupling and inductive noise that can be generated by the sso bus. also, noise generated by the sso bus ne eds to be reduced inside the package. pcbs perform an important function in feeding stable supply voltages to the ic and, at the same time, maintaining signal integrity between devices. key issues that need to considered are as follows: ? power and ground plane design and decoupling network design ? transmission line reflections and terminations
device architecture 2-152 revision 4 selectable skew between output buffer enable/disable time the configurable skew block is used to delay the ou tput buffer assertion (enable) without affecting deassertion (disable) time. figure 2-107 ? block diagram of output enable path figure 2-108 ? timing diagram (option1: bypasses skew circuit) figure 2-109 ? timing diagram (option 2: enables skew circuit) enable (out) skew circuit output enable (from fpga core) i/o output buffers enable (in) mux skew select enable (in) enable (out) less than 0.1 ns less than 0.1 ns enable (in) enable (out) 1.2 ns (typical) less than 0.1 ns
fusion family of mixed signal fpgas revision 4 2-153 at the system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. this circuit, when selected, provides a timing margin that can prevent bus contention and subsequent data loss or transmitter overstress due to transmitter-to- transmitter current shorts. figure 2-110 presents an example of the skew circuit implementation in a bidirectional communication system. figure 2-111 shows how bus cont ention is created, and figure 2- 112 on page 2-154 shows how it can be avoided with the skew circuit. figure 2-110 ? example of implementation of skew circuits in bidirectional transmission systems using fusion devices figure 2-111 ? timing diagram (bypasses skew circuit) transmitter 1: fusion i/o transmitter 2: generic i/o enable(t2) en(b1) en(b2) en(r1) enable(t1) bidirectional data bus transmitter enable/ disable skew or bypass skew routing delay (t1) routing delay (t2) en (b1) en (b2) enable (r1) transmitter 1: on enable (t2) transmitter 2: on enable (t1) bus contention transmitter 1: off transmitter 1: off transmitter 2: off
device architecture 2-154 revision 4 weak pull-up and weak pull-down resistors fusion devices support optional weak pull-up and pull-down resistors for each i/o pin. when the i/o is pulled up, it is connected to the vcci of its corresponding i/o bank. when it is pulled down, it is connected to gnd. refer to table 2-97 on page 2-174 for more information. slew rate control and drive strength fusion devices support output slew rate control: high and low. the high slew rate option is recommended to minimize the pr opagation delay. this hi gh-speed option may introduc e noise into the system if appropriate signal integrity measur es are not adopted. selecting a low slew rate reduces this kind of noise but adds some dela ys in the system. low slew rate is recommended when bus transients are expected. drive str ength should also be selected according to the design requirements and noise immunity of the system. the output slew rate and multiple drive strength controls are available in lvttl/lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 2.5 v / 5.0 v input, lvcmos 1.8 v, and lvcmos 1.5 v. all other i/o standards have a high output slew rate by default. for fusion slew rate and drive strength specifications, refer to the appropriate i/o bank table: ? fusion standard i/o ( table 2-78 on page 2-155 ) ? fusion advanced i/o ( table 2-79 on page 2-155 ) ? fusion pro i/o ( table 2-80 on page 2-155 ) table 2-83 on page 2-158 lists the default values for the above selectable i/o attributes as well as those that are preset for each i/o standard. figure 2-112 ? timing diagram (with skew circuit selected) en (b1) en (b2) transmitter 1: on enable (t2) transmitter 2: on transmitter 2: off enable (t1) result: no bus contention transmitter 1: off transmitter 1: off
fusion family of mixed signal fpgas revision 4 2-155 refer to table 2-78 , table 2-79 , and table 2-80 on page 2-155 for slew and out_drive settings. table 2-81 on page 2-156 and table 2-82 on page 2-157 list the i/o default attributes. table 2-83 on page 2-158 lists the voltages for the supported i/o standards. table 2-78 ? fusion standard i/o st andards?out_drive settings i/o standards out_drive (ma) 246 8 slew lvttl/lvcmos 3.3 v 3333 high low lvcmos 2.5 v 3333 high low lvcmos 1.8 v 33 ? ? high low lvcmos 1.5 v 3 ? ? ? high low table 2-79 ? fusion advanced i/o standards?slew and out_drive settings i/o standards out_drive (ma) 2 4 6 8 12 16 slew lvttl/lvcmos 3.3 v 33333 3 high low lvcmos 2.5 v 33333 ? high low lvcmos 1.8 v 3333 ? ? high low lvcmos 1.5 v 33 ? ? ? ? high low table 2-80 ? fusion pro i/o standards?slew and out_drive settings i/o standards out_drive (ma) slew 2 4 6 8 12 16 24 lvttl/lvcmos 3.3 v 333 3 3 3 3 high low lvcmos 2.5 v 333 3 3 3 3 high low lvcmos 2.5 v/5.0 v 333 3 3 3 3 high low lvcmos 1.8 v 333 3 3 3 ? high low lvcmos 1.5 v 333 3 3 ? ? high low
device architecture 2-156 revision 4 table 2-81 ? fusion pro i/o default attributes i/o standards slew (output only) out_drive (output only) skew (tribuf and bibuf only) res_pull out_load (output only) combine_register in_delay (input only) in_delay_val (input only) schmitt_trigger (input only) lvttl/lvcmo s 3.3 v refer to the following tables for more information: table 2-78 on page 2-155 table 2-79 on page 2-155 table 2-80 on page 2-155 refer to the following tables for more information: table 2-78 on page 2-155 table 2-79 on page 2-155 table 2-80 on page 2-155 off none 35 pf ? off 0 off lvcmos 2.5 v off none 35 pf ? off 0 off lvcmos 2.5/5.0 v off none 35 pf ? off 0 off lvcmos 1.8 v off none 35 pf ? off 0 off lvcmos 1.5 v off none 35 pf ? off 0 off pci (3.3 v) off none 10 pf ? off 0 off pci-x (3.3 v) off none 10 pf ? off 0 off gtl+ (3.3 v) off none 10 pf ? off 0 off gtl+ (2.5 v) off none 10 pf ? off 0 off gtl (3.3 v) off none 10 pf ? off 0 off gtl (2.5 v) off none 10 pf ? off 0 off hstl class i off none 20 pf ? off 0 off hstl class ii off none 20 pf ? off 0 off sstl2 class i and ii off none 30 pf ? off 0 off sstl3 class i and ii off none 30 pf ? off 0 off lvds, blvds, m-lvds off none 0 pf ? off 0 off lvpecl off none 0 pf ? off 0 off
fusion family of mixed signal fpgas revision 4 2-157 table 2-82 ? advanced i/o default attributes i/o standards slew (output only) out_drive (output only) skew (tribuf and bibuf only) res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v refer to the following tables for more information: table 2-78 on page 2-155 table 2-79 on page 2-155 table 2-80 on page 2-155 refer to the following tables for more information: table 2-78 on page 2-155 table 2-79 on page 2-155 table 2-80 on page 2-155 off none 35 pf ? lvcmos 2.5 v off none 35 pf ? lvcmos 2.5/5.0 v off none 35 pf ? lvcmos 1.8 v off none 35 pf ? lvcmos 1.5 v off none 35 pf ? pci (3.3 v) off none 10 pf ? pci-x (3.3 v) off none 10 pf ? lvds, blvds, m-lvds off none ? ? lvpecl off none ? ?
device architecture 2-158 revision 4 table 2-83 ? fusion pro i/o supported standards and corresponding vref and vtt voltages i/o standard input/output supply voltage (vcci_typ) input reference voltage (vref_typ) board termination voltage (vtt_typ) lvttl/lvcmos 3.3 v 3.30 v ? ? lvcmos 2.5 v 2.50 v ? ? lvcmos 2.5 v / 5.0 v input 2.50 v ? ? lvcmos 1.8 v 1.80 v ? ? lvcmos 1.5 v 1.50 v ? ? pci 3.3 v 3.30 v ? ? pci-x 3.3 v 3.30 v ? ? gtl+ 3.3 v 3.30 v 1.00 v 1.50 v gtl+ 2.5 v 2.50 v 1.00 v 1.50 v gtl 3.3 v 3.30 v 0.80 v 1.20 v gtl 2.5 v 2.50 v 0.80 v 1.20 v hstl class i 1.50 v 0.75 v 0.75 v hstl class ii 1.50 v 0.75 v 0.75 v sstl3 class i 3.30 v 1.50 v 1.50 v sstl3 class ii 3.30 v 1.50 v 1.50 v sstl2 class i 2.50 v 1.25 v 1.25 v sstl2 class ii 2.50 v 1.25 v 1.25 v lvds, blvds, m-lvds 2.50 v ? ? lvpecl 3.30 v ? ?
fusion family of mixed signal fpgas revision 4 2-159 i/o software support in the fusion development software, default setti ngs have been defined for the various i/o standards supported. changes can be made to the default sett ings via the use of attributes; however, not all i/o attributes are applicable for all i/o standards. ta b l e 2 - 8 4 and ta b l e 2 - 8 5 list the valid i/o attributes that can be manipulated by the user for each i/o standard. single-ended i/o standards in fusion support up to five different drive strengths. table 2-84 ? fusion standard and advanced i/o attributes vs. i/o standard applications i/o standards slew (output only) out_drive (output only) skew (all macros with oe)* res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v 33 3 3 3 3 lvcmos 2.5 v 33 3 3 3 3 lvcmos 2.5/5.0 v 33 3 3 3 3 lvcmos 1.8 v 33 3 3 3 3 lvcmos 1.5 v 33 3 3 3 3 pci (3.3 v) 333 pci-x (3.3 v) 3333 lvds, blvds, m-lvds 33 lvpecl 3 note: *this feature does not apply to the standard i/o banks, which are the north i/o banks of afs090 and afs250 devices
device architecture 2-160 revision 4 table 2-85 ? fusion pro i/o attributes vs. i/o standard applications i/o standards slew (output only) out_drive (output only) skew (all macros with oe) res_pull out_load (output only) combine_register in_delay (input only) in_delay_val (input only) schmitt_trigger (input only) hot_swappable lvttl/lvcmos 3.3 v 33 33333333 lvcmos 2.5 v 33 33333333 lvcmos 2.5/5.0 v 33 33333333 lvcmos 1.8 v 33 33333333 lvcmos 1.5 v 33 33333333 pci (3.3 v) 33333 pci-x (3.3 v) 333333 gtl+ (3.3 v) 333333 gtl+ (2.5 v) 333333 gtl (3.3 v) 333333 gtl (2.5 v) 333333 hstl class i 333333 hstl class ii 333333 sstl2 class i and ii 333333 sstl3 class i and ii 333333 lvds, blvds, m-lvds 33333 lvpecl 33 3 3
fusion family of mixed signal fpgas revision 4 2-161 user i/o naming convention due to the comprehensive and flexible nature of fusion device user i/os, a naming scheme is used to show the details of the i/o ( figure 2-113 on page 2-161 and figure 2-114 on page 2-162 ). the name identifies to which i/o bank it belongs, as well as the pairing and pin polarity for differential i/os. i/o nomenclature = gmn/iouxwbyvz gmn is only used for i/os that also have ccc access?i.e., global pins. g = global m = global pin location associated with each ccc on the dev ice: a (northwest corner), b (northeast corner), c (east middle), d (southeast corner), e (sou thwest corner), and f (west middle). n = global input mux and pin number of the associated global location m, either a0, a1, a2, b0, b1, b2, c0, c1, or c2. figure 2-22 on page 2-27 shows the three input pins per clock source mux at ccc location m. u = i/o pair number in the bank, starting at 00 from the northwest i/o bank and proceeding in a clockwise direction. x = p (positive) or n (negative) for differential pairs, or r (regular ? single-ended) for the i/os that support single- ended and voltage-referenced i/o standards only. u (pos itive-lvds only) or v (negative-lvds only) restrict the i/o differential pair from be ing selected as an lvpecl pair. w = d (differential pair), p (pair), or s (single-ended). d (differential pair) if both members of the pair are bonded out to adjacent pins or are separated only by one gnd or nc pin; p (pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or s (single-ended) if the i /o pair is not bonded out. for differential (d) pairs, adjacency for ball grid packages means only vertical or horizontal. diagonal adjacency does not meet the requirem ents for a true differential pair. b = bank y = bank number (0?3). the bank number starts at 0 fr om the northwest i/o bank and proceeds in a clockwise direction. v = reference voltage z = minibank number figure 2-113 ? naming conventions of fusion devices with three digital i/o banks ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c" afs090 standard i/o bank analog quads advanced i/o bank advanced i/o bank afs250 bank 3 bank 3 bank 1 bank 1 bank 2 (analog) bank 0
device architecture 2-162 revision 4 figure 2-114 ? naming conventions of fusion devices with four i/o banks afs600 afs1500 bank 4 bank 4 bank 2 bank 2 bank 3 (analog) bank 0 bank 1 ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc/pll "c" pro i/o bank analog quads advnaced i/o bank advanced i/o bank
fusion family of mixed signal fpgas revision 4 2-163 user i/o characteristics timing model figure 2-115 ? timing model operating conditions: ?2 speed, commercial temperature range (t j =70c), worst-case vcc = 1.425 v dq y y dq dq dq y combinational cell combinational cell combinational cell register cell register cell i/o module (non-registered) lvpecl (pro io banks) lvpecl (pro io banks) lvds, blvds, m-lvds (pro io banks) gtl+ 3.3 v y combinational cell y combinational cell y combinational cell lvttl/lvcmos 3.3 v (pro i/o banks) output drive strength = 24 ma high slew rate lvcmos 1.5 v (pro io banks) output drive strength = 12 ma high slew lvttl/lvcmos 3.3 v (pro i/o banks) output drive strength = 12 ma high slew rate iinput lvttl/lvcmos 3.3 v (pro io banks) input lvttl/lvcmos 3.3 v (pro io banks) input lvttl/lvcmos 3.3 v (pro io banks) i/o module (non-registered) i/o module (non-registered) i/o module (non-registered) i/o module (registered) i/o module (registered) i/o module (non-registered) t pd = 0.56 ns t pd = 0.49 ns t dp = 1.60 ns t pd = 0.87 ns t dp = 2.74 ns t pd = 0.51 ns t pd = 0.47 ns t pd = 0.47 ns t oclkq = 0.59 ns t osud = 0.31 ns t py = 0.90 ns t dp = 1.53 ns t dp = 3.30 ns t dp = 2.39 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 0.90 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 1.36 ns t py = 0.90 ns t py = 1.22 ns t iclkq = 0.24 ns t isud = 0.26 ns
device architecture 2-164 revision 4 figure 2-116 ? input buffer timing mode l and delays (example) t py = max(t py (r), t py (f)) t pys = max(t pys (r), t pys (f)) t din = max(t din (r), t din (f)) t py (r) pad y v trip gnd t py (f) v trip 50% 50% vih vcc vil t pys (r) t pys (f) t din (r) din gnd t din (f) 50% 50% vcc pad y t py t pys d clk q i/o interface din t din to array
fusion family of mixed signal fpgas revision 4 2-165 figure 2-117 ? output buffer model and delays (example) t dp (r) pad vol t dp (f) v trip v trip voh vcc d 50% 50% vcc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
device architecture 2-166 revision 4 figure 2-118 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% vcci t zl v trip 50% t hz 90% vcci t zh v trip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls v trip 50% t zhs v trip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% vcc vcc vcc vcci vcc vcc vcc voh vol vol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r). t eout (f))
fusion family of mixed signal fpgas revision 4 2-167 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-86 ? summary of maximum and minimum dc input and ou tput levels applicable to commercial and industrial conditions applicable to pro i/os i/o standard drive strength slew rate vil vih vol voh iol ioh min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 12 12 3.3 v pci per pci specification 3.3 v pci-x per pci-x specification 3.3 v gtl 20 ma 2 high ?0.3 vref ? 0.05 vref + 0.05 3.6 0.4 ? 20 20 2.5 v gtl 20 ma 2 high ?0.3 vref ? 0.05 vref + 0.05 3.6 0.4 ? 20 20 3.3 v gtl+ 35 ma high ?0.3 vref ? 0.1 vref + 0.1 3.6 0.6 ? 35 35 2.5 v gtl+ 33 ma high ?0.3 vref ? 0.1 vref + 0.1 3.6 0.6 ? 33 33 hstl (i) 8 ma high ?0.3 vref ? 0.1 vref + 0.1 3.6 0.4 vcci ? 0.4 8 8 hstl (ii) 15 ma 2 high ?0.3 vref ? 0.1 vref + 0.1 3.6 0.4 vcci ? 0.4 15 15 sstl2 (i) 15 ma high ?0.3 vref ? 0.2 vref + 0.2 3.6 0.54 vcci ? 0.62 15 15 sstl2 (ii) 18 ma high ?0.3 vref ? 0.2 vref + 0.2 3.6 0.35 vcci ? 0.43 18 18 sstl3 (i) 14 ma high ?0.3 vref ? 0.2 vref + 0.2 3.6 0.7 vcci ? 1.1 14 14 sstl3 (ii) 21 ma high ?0.3 vref ? 0.2 vref + 0.2 3.6 0.5 vcci ? 0.9 21 21 notes: 1. currents are measured at 85c junction temperature. 2. output drive strength is below jedec specification. 3. output slew rate can be extracted by the ibis models. table 2-87 ? summary of maximum and minimum dc input and ou tput levels applicable to commercial and industrial conditions applicable to advanced i/os i/o standard drive strength slew rate vil vih vol voh iol ioh min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0. 7 1.7 2.7 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 12 12 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 85c junction temperature.
device architecture 2-168 revision 4 table 2-88 ? summary of maximum and minimum dc input and ou tput levels applicable to commercial and industrial conditions applicable to standard i/os i/o standard drive strength slew rate vil vih vol voh iol ioh min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 2.5 v lvcmos 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 1.5 v lvcmos 2 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0. 25 * vcci 0.75 * vcci 2 2 note: currents are measured at 85c junction temperature. table 2-89 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions applicable to all i/o bank types dc i/o standards commercial 1 industrial 2 iil 3 iih 4 iil 3 iih 4 a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 3.3 v pci 10 10 15 15 3.3 v pci-x 10 10 15 15 3.3 v gtl 10 10 15 15 2.5 v gtl 10 10 15 15 3.3 v gtl+ 10 10 15 15 2.5 v gtl+ 10 10 15 15 hstl (i) 10 10 15 15 hstl (ii) 10 10 15 15 sstl2 (i) 10 10 15 15 sstl2 (ii) 10 10 15 15 sstl3 (i) 10 10 15 15 sstl3 (ii) 10 10 15 15 notes: 1. commercial range (0c < t j < 85c) 2. industrial range (?40c < t j < 100c) 3. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 4. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges.
fusion family of mixed signal fpgas revision 4 2-169 summary of i/o timing characterist ics ? default i/o software settings table 2-90 ? summary of ac measuring points applicable to all i/o bank types standard input reference voltage (vref_typ) board termination voltage (vtt_ref) measuring trip point (vtrip) 3.3 v lvttl / 3.3 v lvcmos ? ? 1.4 v 2.5 v lvcmos ? ? 1.2 v 1.8 v lvcmos ? ? 0.90 v 1.5 v lvcmos ? ? 0.75 v 3.3 v pci ? ? 0.285 * vcci (rr) 0.615 * vcci (ff)) 3.3 v pci-x ? ? 0.285 * vcci (rr) 0.615 * vcci (ff) 3.3 v gtl 0.8 v 1.2 v vref 2.5 v gtl 0.8 v 1.2 v vref 3.3 v gtl+ 1.0 v 1.5 v vref 2.5 v gtl+ 1.0 v 1.5 v vref hstl (i) 0.75 v 0.75 v vref hstl (ii) 0.75 v 0.75 v vref sstl2 (i) 1.25 v 1.25 v vref sstl2 (ii) 1.25 v 1.25 v vref sstl3 (i) 1.5 v 1.485 v vref sstl3 (ii) 1.5 v 1.485 v vref lvds ? ? cross point lvpecl ? ? cross point table 2-91 ? i/o ac parameter definitions parameter definition t dp data to pad delay thr ough the output buffer t py pad to data delay through the input buffer with schmitt trigger disabled t dout data to output buffer delay through the i/o interface t eout enable to output buffer tristate c ontrol delay through the i/o interface t din input buffer to data delay through the i/o interface t pys pad to data delay through the input buffer with schmitt trigger enabled t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
device architecture 2-170 revision 4 table 2-92 ? summary of i/o timing characteris tics ? software default settings commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = i/o standard dependent applicable to pro i/os i/o standard drive strength (ma) slew rate capacitive load (pf) external re sistor (ohm) t dout t dp t din t py t py s t eout t zl t zh t lz t hz t zls t zhs units 3.3 v lvttl/ 3.3 v lvcmos 12 ma high 35 ? 0.49 2.74 0.03 0.90 1. 17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns 2.5 v lvcmos 12 ma high 35 ? 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns 1.8 v lvcmos 12 ma high 35 ? 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns 1.5 v lvcmos 12 ma high 35 ? 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns 3.3 v pci per pci spec high 10 25 2 0.49 2.09 0.03 0.78 1.25 0.32 2. 13 1.49 2.45 2.70 3.80 3.16 ns 3.3 v pci-x per pci-x spec high 10 25 2 0.49 2.09 0.03 0.77 1.17 0.32 2. 13 1.49 2.45 2.70 3.80 3.16 ns 3.3 v gtl 20 ma high 10 25 0.49 1.55 0.03 2.19 ? 0.32 1.52 1.55 0.00 0.00 3.19 3.22 ns 2.5 v gtl 20 ma high 10 25 0.49 1.59 0.03 1.83 ? 0.32 1.61 1.59 0.00 0.00 3.28 3.26 ns 3.3 v gtl+ 35 ma high 10 25 0.49 1.53 0.03 1.19 ? 0.32 1.56 1.53 0.00 0.00 3.23 3.20 ns 2.5 v gtl+ 33 ma high 10 25 0.49 1.65 0.03 1.13 ? 0.32 1.68 1.57 0.00 0.00 3.35 3.24 ns hstl (i) 8 ma high 20 50 0.49 2.37 0.03 1.59 ? 0.32 2.42 2.35 0.00 0.00 4.09 4.02 ns hstl (ii) 15 ma high 20 25 0.49 2.26 0.03 1.59 ? 0.32 2.30 2.03 0.00 0.00 3.97 3.70 ns sstl2 (i) 17 ma high 30 50 0.49 1.59 0.03 1.00 ? 0.32 1.62 1.38 0.00 0.00 3.29 3.05 ns sstl2 (ii) 21 ma high 30 25 0.49 1.62 0.03 1.00 ? 0.32 1.65 1.32 0.00 0.00 3.32 2.99 ns sstl3 (i) 16 ma high 30 50 0.49 1.72 0.03 0.93 ? 0.32 1.75 1.37 0.00 0.00 3.42 3.04 ns sstl3 (ii) 24 ma high 30 25 0.49 1.54 0.03 0.93 ? 0.32 1.57 1.25 0.00 0.00 3.24 2.92 ns lvds 24 ma high ? ? 0.49 1.57 0.03 1.36 ? ? ? ? ? ? ? ? ns lvpecl 24 ma high ? ? 0.49 1.60 0.03 1.22 ? ? ? ? ? ? ? ? ns notes: 1. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-7 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-123 on page 2-200 for connectivity. this resistor is not required during normal operation.
fusion family of mixed signal fpgas revision 4 2-171 table 2-93 ? summary of i/o timing characteris tics ? software default settings commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = i/o standard dependent applicable to advanced i/os i/o standard drive strength (ma) slew rate capacitive load (pf) external re sistor (ohm) t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 3.3 v lvttl/ 3.3 v lvcmos 12 ma high 35 pf ? 0.49 2.64 0.03 0.9 0 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns 2.5 v lvcmos 12 ma high 35 pf ? 0.49 2.6 6 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns 1.8 v lvcmos 12 ma high 35 pf ? 0.49 2.64 0 .03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns 1.5 v lvcmos 12 ma high 35 pf ? 0.49 3.0 5 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns 3.3 v pci per pci spec high 10 pf 25 2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns 3.3 v pci-x per pci-x spec high 10 pf 25 2 0.49 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns lvds 24 ma high ? ? 0.49 1.37 0. 03 1.20 n/a n/a n/a n/a n/a n/a n/a ns lvpecl 24 ma high ? ? 0.49 1.34 0. 03 1.05 n/a n/a n/a n/a n/a n/a n/a ns notes: 1. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-7 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 2-123 on page 2-200 for connectivity. this resistor is not required during normal operation. table 2-94 ? summary of i/o timing characteris tics ? software default settings commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = i/o standard dependent applicable to standard i/os i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor (ohm) t dout t dp t din t py t eout t zl t zh t lz t hz units 3.3 v lvttl/ 3.3 v lvcmos 8 ma high 35 pf ? 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns 2.5 v lvcmos 8 ma high 35pf ? 0.49 3. 56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns 1.8 v lvcmos 4 ma high 35pf ? 0.49 4. 74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns 1.5 v lvcmos 2 ma high 35pf ? 0.49 5. 71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-7 for derating values.
device architecture 2-172 revision 4 detailed i/o dc characteristics table 2-95 ? input capacitance symbol definition conditions min. max. units c in input capacitance vin = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin vin = 0, f = 1.0 mhz 8 pf table 2-96 ? i/o output buffer maximum resistances 1 standard drive strength r pull-down (ohms) 2 r pull-up (ohms) 3 applicable to pro i/o banks 3.3 v lvttl / 3.3 v lvcmos 4 ma 100 300 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 4 ma 100 200 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3 v pci/pci-x per pci/pci-x specification 25 75 3.3 v gtl 20 ma 11 ? 2.5 v gtl 20 ma 14 ? 3.3 v gtl+ 35 ma 12 ? 2.5 v gtl+ 33 ma 15 ? notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on vcc , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the microsemi soc products group website: http://www.microsemi.com/so c/techdocs/models/ibis.html . 2. r (pull-down-max) = volspec / i olspec 3. r (pull-up-max) = (vccimax ? vohspec) / iohspec
fusion family of mixed signal fpgas revision 4 2-173 hstl (i) 8 ma 50 50 hstl (ii) 15 ma 25 25 sstl2 (i) 17 ma 27 31 sstl2 (ii) 21 ma 13 15 sstl3 (i) 16 ma 44 69 sstl3 (ii) 24 ma 18 32 applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3 v pci/pci-x per pci/pci-x specification 25 75 table 2-96 ? i/o output buffer maximum resistances 1 (continued) standard drive strength r pull-down (ohms) 2 r pull-up (ohms) 3 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on vcc , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the microsemi soc products group website: http://www.microsemi.com/so c/techdocs/models/ibis.html . 2. r (pull-down-max) = volspec / i olspec 3. r (pull-up-max) = (vccimax ? vohspec) / iohspec
device architecture 2-174 revision 4 applicable to standard i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 1.5 v lvcmos 2 ma 200 224 table 2-97 ? i/o weak pull-up/pull-down resistances minimum and maximum weak pull-u p/pull-down resistance values vcci r (weak pull-up) 1 (ohms) r (weak pull-down) 2 (ohms) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-up-max) = (vccimax ? vohspec) / i weak pull-up-min 2. r (weak pull-down-max) = volspec / i weak pull-down-min table 2-96 ? i/o output buffer maximum resistances 1 (continued) standard drive strength r pull-down (ohms) 2 r pull-up (ohms) 3 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on vcc , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the microsemi soc products group website: http://www.microsemi.com/so c/techdocs/models/ibis.html . 2. r (pull-down-max) = volspec / i olspec 3. r (pull-up-max) = (vccimax ? vohspec) / iohspec
fusion family of mixed signal fpgas revision 4 2-175 table 2-98 ? i/o short currents iosh/iosl drive strength iosh (ma)* iosl (ma)* applicable to pro i/o banks 3.3 v lvttl / 3.3 v lvcmos 4 ma 25 27 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 2.5 v lvcmos 4 ma 16 18 8 ma 32 37 12 ma 65 74 16 ma 83 87 24 ma 169 124 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 45 51 12 ma 91 74 16 ma 91 74 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 6 ma 32 39 8 ma 66 55 12 ma 66 55 applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 12 ma 103 109 16 ma 132 127 24 ma 268 181 note: *t j = 100c
device architecture 2-176 revision 4 the length of time an i/o can withstand iosh/iosl events depends on the junc tion temperature. the reliability data below is based on a 3.3 v, 36 ma i/o setting, which is the worst case for this type of analysis. for example, at 100c, the short current condition would have to be sustained for more than six months to cause a reliability concern. the i/o design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 12 ma 65 74 16 ma 83 87 24 ma 169 124 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 45 51 12 ma 91 74 16 ma 91 74 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 6 ma 32 39 8 ma 66 55 12 ma 66 55 3.3 v pci/pci-x per pci/pci-x specification 103 109 applicable to standard i/o banks 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 1.5 v lvcmos 2 ma 13 16 table 2-98 ? i/o short currents io sh/iosl (continued) drive strength iosh (ma)* iosl (ma)* note: *t j = 100c
fusion family of mixed signal fpgas revision 4 2-177 table 2-99 ? short current event dura tion before failure temperature time before failure ?40c >20 years 0c >20 years 25c >20 years 70c 5 years 85c 2 years 100c 6 months table 2-100 ? schmitt trigger input hysteresis hysteresis voltage value (typ.) for schmitt mode input buffers input buffer configuration hysteresis value (typ.) 3.3 v lvttl/lvcmos/pci/pci-x (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmitt trigger mode) 80 mv 1.5 v lvcmos (schmitt trigger mode) 60 mv table 2-101 ? i/o input rise time, fall time, and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos (schmitt trigger disabled) no requirement 10 ns* 20 years (100c) lvttl/lvcmos (schmitt trigger enabled) no requirement no requirement, but input noise voltage cannot exceed schmitt hysteresis 20 years (100c) hstl/sstl/gtl no requirement 10 ns* 10 years (100c) lvds/blvds/m-lvds/lvpecl no re quirement 10 ns* 10 years (100c) note: *the maximum input rise/fall time is related only to the noise induced into the input buffer trace. if the noise is low, the rise time and fall time of input buffers, when schmitt trigger is disabled, can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. microsemi recommends signal integrity ev aluation/characterization of the system to ensure there is no excessive noise coupling into input signals.
device architecture 2-178 revision 4 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and pu sh-pull output buffer. the 3.3 v lvcmos standard is supported as part of the 3.3 v lvttl support. table 2-102 ? minimum and maximum dc input and output levels 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 applicable to pro i/o banks 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 applicable to standard i/o banks 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-119 ? ac loading table 2-103 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ.) (v) c load (pf) 03.31.4?35 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point test point enable path data path 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
fusion family of mixed signal fpgas revision 4 2-179 timing characteristics table 2-104 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/os drive strength spee d grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29 ns ?1 0.56 9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60 ns ?2 0.49 8.22 0.03 0.90 1.17 0. 32 8.37 6.76 2.01 1.82 10.04 8.43 ns 8 ma std. 0.66 7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68 ns ?1 0.56 6.69 0.04 1.02 1.33 0. 36 6.81 5.48 2.58 2.61 8.71 7.38 ns ?2 0.49 5.87 0.03 0.90 1.17 0. 32 5.98 4.81 2.27 2.29 7.65 6.48 ns 12 ma std. 0.66 6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26 ns ?1 0.56 5.13 0.04 1.02 1.33 0. 36 5.22 4.27 2.79 2.95 7.12 6.17 ns ?2 0.49 4.50 0.03 0.90 1.17 0. 32 4.58 3.75 2.45 2.59 6.25 5.42 ns 16 ma std. 0.66 5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96 ns ?1 0.56 4.78 0.04 1.02 1.33 0. 36 4.87 4.02 2.83 3.04 6.77 5.92 ns ?2 0.49 4.20 0.03 0.90 1.17 0. 32 4.27 3.53 2.48 2.67 5.94 5.20 ns 24 ma std. 0.66 5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93 ns ?1 0.56 4.46 0.04 1.02 1.33 0. 36 4.54 3.99 2.88 3.37 6.44 5.89 ns ?2 0.49 3.92 0.03 0.90 1.17 0. 32 3.99 3.50 2.53 2.96 5.66 5.17 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-180 revision 4 table 2-105 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eou t t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 7.88 0.04 1.20 1.57 0. 43 8.03 6.70 2.69 2.59 10.26 8.94 ns ?1 0.56 6.71 0.04 1. 02 1.33 0.36 6.83 5.70 2. 29 2.20 8.73 7.60 ns ?2 0.49 5.89 0.03 0. 90 1.17 0.32 6.00 5.01 2. 01 1.93 7.67 6.67 ns 8 ma std. 0.66 5.08 0.04 1.20 1.57 0. 43 5.17 4.14 3.05 3.21 7.41 6.38 ns ?1 0.56 4.32 0.04 1. 02 1.33 0.36 4.40 3.52 2. 59 2.73 6.30 5.43 ns ?2 0.49 3.79 0.03 0. 90 1.17 0.32 3.86 3.09 2. 28 2.40 5.53 4.76 ns 12 ma std. 0.66 3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11 ns ?1 0.56 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34 ns ?2 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns 16 ma std. 0.66 3.46 0.04 1.20 1.57 0. 43 3.53 2.61 3.33 3.72 5.76 4.84 ns ?1 0.56 2.95 0.04 1. 02 1.33 0.36 3.00 2.22 2. 83 3.17 4.90 4.12 ns ?2 0.49 2.59 0.03 0. 90 1.17 0.32 2.63 1.95 2. 49 2.78 4.30 3.62 ns 24 ma std. 0.66 3.21 0.04 1.20 1.57 0. 43 3.27 2.16 3.39 4.13 5.50 4.39 ns ?1 0.56 2.73 0.04 1. 02 1.33 0.36 2.78 1.83 2. 88 3.51 4.68 3.74 ns ?2 0.49 2.39 0.03 0. 90 1.17 0.32 2.44 1.61 2. 53 3.08 4.11 3.28 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-181 table 2-106 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 10.26 0.04 1.20 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns ?1 0.56 8.72 0.04 1.02 0.36 8.89 7.57 2.25 2.09 10.79 9.47 ns ?2 0.49 7.66 0.03 0.90 0.32 7.80 6.64 1.98 1.83 9.47 8.31 ns 8 ma std. 0.66 7.27 0.04 1.20 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns ?1 0.56 6.19 0.04 1.02 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns ?2 0.49 5.43 0.03 0.90 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns 12 ma std. 0.66 5.58 0.04 1.20 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns ?1 0.56 4.75 0.04 1.02 0.36 4.84 4.14 2.73 2.91 6.74 6.05 ns ?2 0.49 4.17 0.03 0.90 0.32 4.24 3.64 2.39 2.55 5.91 5.31 ns 16 ma std. 0.66 5.21 0.04 1.20 0.43 5.30 4.56 3.26 3.51 7.54 6.80 ns ?1 0.56 4.43 0.04 1.02 0.36 4.51 3.88 2.77 2.99 6.41 5.79 ns ?2 0.49 3.89 0.03 0.90 0.32 3.96 3.41 2.43 2.62 5.63 5.08 ns 24 ma std. 0.66 4.85 0.04 1.20 0.43 4.94 4.54 3.32 3.88 7.18 6.78 ns ?1 0.56 4.13 0.04 1.02 0.36 4.20 3.87 2.82 3.30 6.10 5.77 ns ?2 0.49 3.62 0.03 0.90 0.32 3.69 3.39 2.48 2.90 5.36 5.06 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-182 revision 4 table 2-107 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 7.66 0. 04 1.20 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns ?1 0.56 6.51 0.04 1. 02 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns ?2 0.49 5.72 0.03 0. 90 0.32 5.82 4.92 1.98 1.95 7.49 6.59 ns 8 ma std. 0.66 4.91 0. 04 1.20 0.43 5.00 4.07 2. 99 3.20 7.23 6.31 ns ?1 0.56 4.17 0.04 1. 02 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns ?2 0.49 3.66 0.03 0. 90 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns 12 ma std. 0.66 3.53 0.04 1.20 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns ?1 0.56 3.00 0.04 1.02 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns ?2 0.49 2.64 0.03 0.90 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns 16 ma std. 0.66 3.33 0. 04 1.20 0.43 3.39 2.56 3. 26 3.68 5.63 4.80 ns ?1 0.56 2.83 0.04 1. 02 0.36 2.89 2.18 2.77 3.13 4.79 4.08 ns ?2 0.49 2.49 0.03 0. 90 0.32 2.53 1.91 2.44 2.75 4.20 3.58 ns 24 ma std. 0.66 3.08 0. 04 1.20 0.43 3.13 2.12 3. 32 4.06 5.37 4.35 ns ?1 0.56 2.62 0.04 1. 02 0.36 2.66 1.80 2.83 3.45 4.57 3.70 ns ?2 0.49 2.30 0.03 0. 90 0.32 2.34 1.58 2.48 3.03 4.01 3.25 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-108 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2. 07 2.04 ns ?1 0.56 8.05 0.04 0.85 0. 36 8.20 7.27 1.76 1.73 ns ?2 0.49 7.07 0.03 0.75 0. 32 7.20 6.38 1.55 1.52 ns 4 ma std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2. 07 2.04 ns ?1 0.56 8.05 0.04 0.85 0. 36 8.20 7.27 1.76 1.73 ns ?2 0.49 7.07 0.03 0.75 0. 32 7.20 6.38 1.55 1.52 ns 6 ma std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2. 40 2.57 ns ?1 0.56 5.59 0.04 0.85 0. 36 5.69 5.09 2.04 2.19 ns ?2 0.49 4.91 0.03 0.75 0. 32 5.00 4.47 1.79 1.92 ns 8 ma std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2. 40 2.57 ns ?1 0.56 5.59 0.04 0.85 0. 36 5.69 5.09 2.04 2.19 ns ?2 0.49 4.91 0.03 0.75 0. 32 5.00 4.47 1.79 1.92 ns note: for the derating values at spec ific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-183 table 2-109 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns ?1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns ?2 2 0.49 5.28 0.03 0.75 0.32 5. 37 4.65 1.55 1.60 ns 4 ma std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns ?1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns ?2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns 6 ma std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns ?1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns ?2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns 8 ma std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns ?1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns ?2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to ta ble 3-7 o n page 3-9 .
device architecture 2-184 revision 4 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. table 2-110 ? minimum and maximum dc input and output levels 2.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 applicable to pro i/o banks 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 16 ma ?0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10 24 ma ?0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 10 10 16 ma ?0.3 0.7 1.7 2.7 0.7 1.7 16 16 87 83 10 10 24 ma ?0.3 0.7 1.7 2.7 0.7 1.7 24 24 124 169 10 10 applicable to standard i/o banks 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-120 ? ac loading table 2-111 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ.) (v) c load (pf) 02.51.2?35 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point test point enable path data path 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
fusion family of mixed signal fpgas revision 4 2-185 timing characteristics table 2-112 ? 2.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85 ns ?1 0.51 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78 ns ?2 0.45 8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34 ns 8 ma std. 0.60 8.73 0.04 1.51 1.66 0. 43 8.89 8.01 3.10 2.93 11.13 10.25 ns ?1 0.51 7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72 ns ?2 0.45 6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65 ns 12 ma std. 0.66 6.77 0.04 1.51 1.66 0. 43 6.90 6.11 3.37 3.39 9.14 8.34 ns ?1 0.56 5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10 ns ?2 0.49 5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23 ns 16 ma std. 0.66 6.31 0.04 1.51 1.66 0. 43 6.42 5.73 3.42 3.52 8.66 7.96 ns ?1 0.56 5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77 ns ?2 0.49 4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95 ns 24 ma std. 0.66 5.93 0.04 1.51 1.66 0. 43 6.04 5.70 3.49 4.00 8.28 7.94 ns ?1 0.56 5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75 ns ?2 0.49 4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-186 revision 4 table 2-113 ? 2.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.60 8.82 0.04 1.51 1.66 0. 43 8.13 8.82 2.72 2.29 10.37 11.05 ns ?1 0.51 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40 ns ?2 0.45 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25 ns 8 ma std. 0.60 5.27 0.04 1.51 1.66 0. 43 5.27 5.27 3.10 3.03 7.50 7.51 ns ?1 0.51 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38 ns ?2 0.45 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61 ns 12 ma std. 0.66 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73 ns ?1 0.56 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87 ns ?2 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns 16 ma std. 0.66 3.53 0.04 1.51 1.66 0. 43 3.59 3.12 3.42 3.62 5.83 5.35 ns ?1 0.56 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55 ns ?2 0.49 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00 ns 24 ma std. 0.66 3.26 0.04 1.51 1.66 0. 43 3.32 2.48 3.49 4. 11 5.56 4.72 ns ?1 0.56 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01 ns ?2 0.49 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-187 table 2-114 ? 2.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns ?1 0.56 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns ?2 0.49 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns 8 ma std. 0.66 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns ?1 0.56 6.77 0.04 1.11 0.36 6. 90 6.65 2.59 2.46 8.80 8.55 ns ?2 0.49 5.94 0.03 0.98 0.32 6. 05 5.84 2.28 2.16 7.72 7.50 ns 12 ma std. 0.66 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.56 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.26 6.94 ns ?2 0.49 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns 16 ma std. 0.66 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.56 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.26 6.94 ns ?2 0.49 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns 24 ma std. 0.66 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.56 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.26 6.94 ns ?2 0.49 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-188 revision 4 table 2-115 ? 2.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma std. 0.66 8.66 0.04 1.31 0.43 7. 83 8.66 2.68 2.30 10.07 10.90 ns ?1 0.56 7.37 0.04 1.11 0.36 6. 66 7.37 2.28 1.96 8.56 9.27 ns ?2 0.49 6.47 0.03 0.98 0.32 5. 85 6.47 2.00 1.72 7.52 8.14 ns 8 ma std. 0.66 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns ?1 0.56 4.39 0.04 1.11 0.36 4. 28 4.39 2.59 2.55 6.19 6.30 ns ?2 0.49 3.86 0.03 0.98 0.32 3. 76 3.86 2.28 2.24 5.43 5.53 ns 12 ma std. 0.66 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns ?1 0.56 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns ?2 0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns 16 ma std. 0.66 3.35 0.04 1.31 0.43 3.41 3.06 3.36 3.55 5.65 5.30 ns ?1 0.56 2.85 0.04 1.11 0.36 2. 90 2.60 2.86 3.02 4.81 4.51 ns ?2 0.49 2.50 0.03 0.98 0.32 2. 55 2.29 2.51 2.65 4.22 3.96 ns 24 ma std. 0.66 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns ?1 0.56 3.03 0.04 1.11 0.36 3. 08 2.92 2.81 2.92 4.99 4.82 ns ?2 0.49 2.66 0.03 0.98 0.32 2. 71 2.56 2.47 2.57 4.38 4.23 ns note: for the derating values at spec ific junction temperature and voltage supply levels, refer to ta ble 3-7 o n page 3-9 . table 2-116 ? 2.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns ?1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns ?2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns 4 ma std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns ?1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns ?2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns 6 ma std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns ?1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns ?2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns 8 ma std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns ?1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns ?2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-189 table 2-117 ? 2.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns ?1 0.56 6.98 0.04 1.10 0. 36 6.16 6.98 1.73 1.62 ns ?2 0.49 6.13 0.03 0.96 0. 32 5.41 6.13 1.52 1.43 ns 4 ma std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns ?1 0.56 6.98 0.04 1.10 0. 36 6.16 6.98 1.73 1.62 ns ?2 0.49 6.13 0.03 0.96 0. 32 5.41 6.13 1.52 1.43 ns 6 ma std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns ?1 0.56 4.05 0.04 1.10 0. 36 3.87 4.05 2.03 2.17 ns ?2 0.49 3.56 0.03 0.96 0. 32 3.40 3.56 1.78 1.91 ns 8 ma std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns ?1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns ?2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-190 revision 4 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and push-pull output buffer. table 2-118 ? minimum and maximum dc input and output levels 1.8 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 applicable to pro i/o banks 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 8 8 51 45 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 12 12 74 91 10 10 16 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 16 16 74 91 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 8 8 51 45 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 12 12 74 91 10 10 16 ma ?0.3 0.35 * vcci 0.65 * vcci 1.9 0.45 vcci ? 0.45 16 16 74 91 10 10 applicable to standard i/o banks 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 22 17 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-121 ? ac loading table 2-119 ? ac waveforms, measuring points, and capacitive loads input low (v) input low (v) measuring point* (v) vref (typ.) (v) c load (pf) 01.80.9?35 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point test point enable path data path 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
fusion family of mixed signal fpgas revision 4 2-191 timing characteristics table 2-120 ? 1.8 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07 ns ?1 0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37 ns ?2 0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50 ns 4 ma std. 0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99 ns ?1 0.56 9.69 0.04 1.23 1.62 0.36 9. 87 9.15 2.77 2.36 11.77 11.05 ns ?2 0.49 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70 ns 8 ma std. 0.66 8.97 0.04 1.45 1.91 0. 43 9.14 8.10 3.57 3.36 11.37 10.33 ns ?1 0.56 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79 ns ?2 0.49 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72 ns 12 ma std. 0.66 8.35 0.04 1.45 1.91 0. 43 8.50 7.59 3.64 3.52 10.74 9.82 ns ?1 0.56 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35 ns ?2 0.49 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33 ns 16 ma std. 0.66 7.94 0.04 1.45 1.91 0. 43 8.09 7.56 3.74 4.11 10.32 9.80 ns ?1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns ?2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-192 revision 4 table 2-121 ? 1.8 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 12.10 0.04 1.45 1.91 0. 43 9.59 12.10 2.78 1.64 11.83 14.34 ns ?1 0.56 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20 ns ?2 0.49 9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71 ns 4 ma std. 0.66 7.05 0.04 1.45 1.91 0. 43 6.20 7.05 3.25 2.86 8.44 9.29 ns ?1 0.56 6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90 ns ?2 0.49 5.27 0.03 1.08 1.42 0.32 4.63 5.27 2.43 2.14 6.30 6.94 ns 8 ma std. 0.66 4.52 0.04 1.45 1.91 0.43 4.47 4.52 3.57 3.47 6.70 6.76 ns ?1 0.56 3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75 ns ?2 0.49 3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05 ns 12 ma std. 0.66 4.12 0.04 1.45 1.91 0. 43 4.20 3.99 3.63 3.62 6.43 6.23 ns ?1 0.56 3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30 ns ?2 0.49 3.08 0.03 1.08 1.42 0.32 3.14 2.98 2.71 2.71 4.81 4.65 ns 16 ma std. 0.66 3.80 0.04 1.45 1.91 0. 43 3.87 3.09 3.73 4.24 6.10 5.32 ns ?1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns ?2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-193 table 2-122 ? 1.8 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 15.53 0.04 1.31 0.43 1 4.11 15.53 2.78 1.60 16.35 17.77 ns ?1 0.56 13.21 0.04 1.11 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns ?2 2 0.49 11.60 0.03 0.98 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns 4 ma std. 0.66 10.48 0.04 1.31 0.43 10.41 10.48 3.23 2.73 12.65 12.71 ns ?1 0.56 8.91 0.04 1. 11 0.36 8.86 8.91 2.75 2. 33 10.76 10.81 ns ?2 0.49 7.82 0.03 0.98 0.32 7. 77 7.82 2.41 2.04 9.44 9.49 ns 8 ma std. 0.66 8.05 0. 04 1.31 0.43 8.20 7.84 3.54 3.27 10.43 10.08 ns ?1 0.56 6.85 0.04 1.11 0.36 6. 97 6.67 3.01 2.78 8.88 8.57 ns ?2 0.49 6.01 0.03 0.98 0.32 6. 12 5.86 2.64 2.44 7.79 7.53 ns 12 ma std. 0.66 7.50 0. 04 1.31 0.43 7.64 7.30 3. 61 3.41 9.88 9.53 ns ?1 0.56 6.38 0.04 1.11 0.36 6. 50 6.21 3.07 2.90 8.40 8.11 ns ?2 0.49 5.60 0.03 0.98 0.32 5. 71 5.45 2.69 2.55 7.38 7.12 ns 16 ma std. 0.66 7.29 0. 04 1.31 0.43 7.23 7.29 3. 71 3.95 9.47 9.53 ns ?1 0.56 6.20 0.04 1.11 0.36 6. 15 6.20 3.15 3.36 8.06 8.11 ns ?2 0.49 5.45 0.03 0.98 0.32 5. 40 5.45 2.77 2.95 7.07 7.12 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-194 revision 4 table 2-123 ? 1.8 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 11.86 0.04 1.22 0.43 9.14 11.86 2.77 1.66 11.37 14.10 ns ?1 0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns ?2 0.49 8.86 0.03 0.91 0.32 6. 82 8.86 2.07 1.24 8.49 10.53 ns 4 ma std. 0.66 6.91 0.04 1.22 0.43 5.86 6.91 3.22 2.84 8.10 9.15 ns ?1 0.56 5.88 0.04 1.04 0.36 4. 99 5.88 2.74 2.41 6.89 7.78 ns ?2 0.49 5.16 0.03 0.91 0.32 4. 38 5.16 2.41 2.12 6.05 6.83 ns 8 ma std. 0.66 4.45 0.04 1.22 0.43 4.18 4.45 3.53 3.38 6.42 6.68 ns ?1 0.56 3.78 0.04 1.04 0.36 3.56 3.78 3.00 2.88 5.46 5.69 ns ?2 0.49 3.32 0.03 0.91 0.32 3.12 3.32 2.64 2.53 4.79 4.99 ns 12 ma std. 0.66 3.92 0.04 1.22 0.43 3.93 3.92 3.60 3.52 6.16 6.16 ns ?1 0.56 3.34 0.04 1.04 0.36 3. 34 3.34 3.06 3.00 5.24 5.24 ns ?2 0.49 2.93 0.03 0.91 0.32 2. 93 2.93 2.69 2.63 4.60 4.60 ns 16 ma std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns ?1 0.56 3.01 0.04 1.04 0.36 3. 06 2.59 3.15 3.47 4.96 4.49 ns ?2 0.49 2.64 0.03 0.91 0.32 2. 69 2.27 2.76 3.05 4.36 3.94 ns note: for the derating values at spec ific junction temperature and voltage supply levels, refer to ta ble 3-7 o n page 3-9 . table 2-124 ? 1.8 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 15.01 0.04 1.20 0.43 13.15 15.01 1.99 1.99 ns ?1 0.56 12.77 0.04 1.02 0.36 11.19 12.77 1.70 1.70 ns ?2 0.49 11.21 0.03 0.90 0.32 9.82 11.21 1.49 1.49 ns 4 ma std. 0.66 10.10 0.04 1.20 0.43 9.55 10.10 2.41 2.37 ns ?1 0.56 8.59 0.04 1.02 0.36 8.13 8.59 2.05 2.02 ns ?2 0.49 7.54 0.03 0.90 0.32 7.13 7.54 1.80 1.77 ns note: for the derating values at spec ific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-195 table 2-125 ? 1.8 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 11.21 0.04 1.20 0.43 8.53 11.21 1.99 1.21 ns ?1 0.56 9.54 0.04 1.02 0.36 7.26 9.54 1.69 1.03 ns ?2 0.49 8.37 0.03 0.90 0.32 6.37 8.37 1.49 0.90 ns 4 ma std. 0.66 6.34 0.04 1.20 0.43 5.38 6.34 2.41 2.48 ns ?1 0.56 5.40 0.04 1.02 0.36 4.58 5.40 2.05 2.11 ns ?2 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-196 revision 4 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and push-pull output buffer. table 2-126 ? minimum and maximum dc input and output levels 1.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 applicable to pro i/o banks 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 16 13 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 4 4 33 25 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 6 6 39 32 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 8 8 55 66 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 12 12 55 66 10 10 applicable to advanced i/o banks 2 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 2 2 16 13 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 4 4 33 25 10 10 6 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 6 6 39 32 10 10 8 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 8 8 55 66 10 10 12 ma ?0.3 0.35 * vcci 0.65 * vcci 1.575 0.25 * vcci 0.75 * vcci 12 12 55 66 10 10 applicable to pro i/o banks 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 16 13 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-122 ? ac loading table 2-127 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) meas uring point* (v) vref (typ.) (v) c load (pf) 0 1.5 0.75 ? 35 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point test point enable path data path 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
fusion family of mixed signal fpgas revision 4 2-197 timing characteristics table 2-128 ? 1.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 14.11 0.04 1.70 2.14 0. 43 14.37 13.14 3.40 2. 68 16.61 15.37 ns ?1 0.56 12.00 0.04 1.44 1.82 0.36 12. 22 11.17 2.90 2.28 14.13 13.08 ns ?2 0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48 ns 4 ma std. 0.66 11.23 0.04 1.70 2.14 0 .43 11.44 9.87 3.77 3.36 13.68 12.10 ns ?1 0.56 9.55 0.04 1.44 1.82 0.36 9. 73 8.39 3.21 2.86 11.63 10.29 ns ?2 0.49 8.39 0.03 1.27 1.60 0.32 8. 54 7.37 2.81 2.51 10.21 9.04 ns 8 ma std. 0.66 10.45 0.04 1.70 2.14 0 .43 10.65 9.24 3.84 3.55 12.88 11.48 ns ?1 0.56 8.89 0.04 1.44 1.82 0.36 9. 06 7.86 3.27 3.02 10.96 9.76 ns ?2 0.49 7.81 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57 ns 12 ma std. 0.66 10.02 0.04 1.70 2.14 0 .43 10.20 9.23 3.97 4.22 12.44 11.47 ns ?1 0.56 8.52 0.04 1.44 1.82 0.36 8. 68 7.85 3.38 3.59 10.58 9.75 ns ?2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns note: for the derating values at specific junction te mperature and voltage supp ly levels, refer to table 3-7 on page 3-9 . table 2-129 ? 1.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to pro i/os drive strength speed grade t dout t dp t din t py t pys t eou t t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 8.53 0.04 1.70 2.14 0. 43 7.26 8.53 3.39 2.79 9.50 10.77 ns ?1 0.56 7.26 0.04 1.44 1.82 0.36 6. 18 7.26 2.89 2.37 8.08 9.16 ns ?2 0.49 6.37 0.03 1.27 1.60 0.32 5. 42 6.37 2.53 2.08 7.09 8.04 ns 4 ma std. 0.66 5.41 0.04 1.70 2.14 0. 43 5.22 5.41 3.75 3.48 7.45 7.65 ns ?1 0.56 4.60 0.04 1.44 1.82 0.36 4. 44 4.60 3.19 2.96 6.34 6.50 ns ?2 0.49 4.04 0.03 1.27 1.60 0.32 3. 89 4.04 2.80 2.60 5.56 5.71 ns 8 ma std. 0.66 4.80 0.04 1.70 2.14 0. 43 4.89 4.75 3.83 3.67 7.13 6.98 ns ?1 0.56 4.09 0.04 1.44 1.82 0.36 4. 16 4.04 3.26 3.12 6.06 5.94 ns ?2 0.49 3.59 0.03 1.27 1.60 0.32 3. 65 3.54 2.86 2.74 5.32 5.21 ns 12 ma std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns ?1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns ?2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-198 revision 4 table 2-130 ? 1.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 12.78 0. 04 1.31 0.43 12.81 12.78 3.40 2.64 15.05 15.02 ns ?1 0.56 10.87 0.04 1. 11 0.36 10.90 10.87 2.89 2. 25 12.80 12.78 ns ?2 0.49 9.55 0.03 0. 98 0.32 9.57 9.55 2.54 1. 97 11.24 11.22 ns 4 ma std. 0.66 10.01 0. 04 1.31 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns ?1 0.56 8.51 0.04 1. 11 0.36 8.67 8.12 3.19 2. 78 10.57 10.02 ns ?2 0.49 7.47 0.03 0.98 0.32 7. 61 7.13 2.80 2.44 9.28 8.80 ns 8 ma std. 0.66 9.33 0. 04 1.31 0.43 9.51 8.89 3.83 3.43 11.74 11.13 ns ?1 0.56 7.94 0.04 1.11 0.36 8. 09 7.56 3.26 2.92 9.99 9.47 ns ?2 0.49 6.97 0.03 0.98 0.32 7. 10 6.64 2.86 2.56 8.77 8.31 ns 12 ma std. 0.66 8.91 0. 04 1.31 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns ?1 0.56 7.58 0.04 1.11 0.36 7. 72 7.57 3.36 3.44 9.62 9.47 ns ?2 0.49 6.65 0.03 0.98 0.32 6. 78 6.64 2.95 3.02 8.45 8.31 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-131 ? 1.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to advanced i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma std. 0.66 8.36 0.04 1.44 0.43 6.82 8.36 3.39 2.77 9.06 10.60 ns ?1 0.56 7.11 0.04 1.22 0.36 5. 80 7.11 2.88 2.35 7.71 9.02 ns ?2 0.49 6.24 0.03 1.07 0.32 5. 10 6.24 2.53 2.06 6.76 7.91 ns 4 ma std. 0.66 5.31 0.04 1.44 0.43 4.85 5.31 3.74 3.40 7.09 7.55 ns ?1 0.56 4.52 0.04 1.22 0.36 4. 13 4.52 3.18 2.89 6.03 6.42 ns ?2 0.49 3.97 0.03 1.07 0.32 3. 62 3.97 2.79 2.54 5.29 5.64 ns 8 ma std. 0.66 4.67 0.04 1.44 0.43 4.55 4.67 3.82 3.56 6.78 6.90 ns ?1 0.56 3.97 0.04 1.22 0.36 3. 87 3.97 3.25 3.03 5.77 5.87 ns ?2 0.49 3.49 0.03 1.07 0.32 3. 40 3.49 2.85 2.66 5.07 5.16 ns 12 ma std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns ?1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns ?2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns note: for the derating values at spec ific junction temperature and voltage supply levels, refer to ta ble 3-7 o n page 3-9 .
fusion family of mixed signal fpgas revision 4 2-199 table 2-132 ? 1.5 v lvcmos low slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 12.33 0.04 1.42 0.43 11.79 12.33 2.45 2.32 ns ?1 0.56 10.49 0.04 1.21 0.36 10.03 10.49 2.08 1.98 ns ?2 0.49 9.21 0.03 1.06 0.32 8.81 9.21 1.83 1.73 ns note: for the derating values at specific junction temperature and voltage su pply levels, refer to table 3-7 on page 3-9 . table 2-133 ? 1.5 v lvcmos high slew commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v applicable to standard i/os drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma std. 0.66 7.65 0.04 1.42 0.43 6.31 7.65 2.45 2.45 ns ?1 0.56 6.50 0.04 1.21 0.36 5.37 6.50 2.08 2.08 ns ?2 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to ta ble 3-7 o n page 3-9 .
device architecture 2-200 revision 4 3.3 v pci, 3.3 v pci-x the peripheral component interface for 3.3 v st andard specifies support for 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pci/pci-x specificat ions for the datapath; microsemi loadings for enable path characterization are described in figure 2-123 . ac loadings are defined per pci/pci-x specifications for the data path; microsemi loading for tristate is described in table 2-135 . table 2-134 ? minimum and maximum dc input and output levels 3.3 v pci/pci-x vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 per pci specification per pci curves 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-123 ? ac loading test point enable path r = 1 k test point data path r = 25 r to vcci for t dp (f) r to gnd for t dp (r) r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 10 pf for t zh / t zhs / t zl / t zls 10 pf for t hz / t lz table 2-135 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) c load (pf) 0 3.3 0.285 * vcci for t dp(r) 0.615 * vcci for t dp(f) ?10 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points.
fusion family of mixed signal fpgas revision 4 2-201 timing characteristics table 2-136 ? 3.3 v pci/pci-x commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/os speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.81 0.04 1.05 1.67 0. 43 2.86 2.00 3.28 3.61 5.09 4.23 ns ?1 0.56 2.39 0.04 0.89 1.42 0. 36 2.43 1.70 2.79 3.07 4.33 3.60 ns ?2 0.49 2.09 0.03 0.78 1.25 0. 32 2.13 1.49 2.45 2.70 3.80 3.16 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . table 2-137 ? 3.3 v pci/pci-x commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to advanced i/os speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.68 0.04 0.86 0.43 2. 73 1.95 3.21 3.58 4.97 4.19 0.66 ns ?1 0.56 2.28 0.04 0.73 0.36 2. 32 1.66 2.73 3.05 4.22 3.56 0.56 ns ?2 0.49 2.00 0.03 0.65 0.32 2. 04 1.46 2.40 2.68 3.71 3.13 0.49 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-202 revision 4 voltage referenced i/o characteristics 3.3 v gtl gunning transceiver logic is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. t he vcci pin should be connected to 3.3 v. timing characteristics table 2-138 ? minimum and maximum dc input and output levels 3.3 v gtl vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 20 ma 3 ?0.3 vref ? 0.05 vref + 0.05 3.6 0.4 ? 20 20 181 268 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-124 ? ac loading table 2-139 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.05 vref + 0.05 0.8 0.8 1.2 10 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 10 pf 25 gtl vtt table 2-140 ? 3.3 v gtl commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v, vref = 0.8 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.08 0.04 2.93 0.43 2.04 2.08 4.27 4.31 ns ?1 0.56 1.77 0.04 2.50 0.36 1.73 1.77 3.63 3.67 ns ?2 0.49 1.55 0.03 2.19 0.32 1.52 1.55 3.19 3.22 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-203 2.5 v gtl gunning transceiver logic is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. t he vcci pin should be connected to 2.5 v. timing characteristics table 2-141 ? minimum and maximum dc input and output levels 2.5 gtl vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 20 ma 3 ?0.3 vref ? 0.05 vref + 0.05 3.6 0.4 ? 20 20 124 169 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-125 ? ac loading table 2-142 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring po int* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.05 vref + 0.05 0.8 0.8 1.2 10 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 10 pf 25 gtl vtt table 2-143 ? 2.5 v gtl commercial temperature range conditions: tj = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v, vref = 0.8 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.13 0.04 2.46 0.43 2.16 2.13 4.40 4.36 ns ?1 0.56 1.81 0.04 2.09 0.36 1.84 1.81 3.74 3.71 ns ?2 0.49 1.59 0.03 1.83 0.32 1.61 1.59 3.28 3.26 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-204 revision 4 3.3 v gtl+ gunning transceiver logic plus is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. the vcci pin should be connected to 3.3 v. timing characteristics table 2-144 ? minimum and maximum dc input and output levels 3.3 v gtl+ vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 35 ma ?0.3 vref ? 0.1 vref + 0.1 3.6 0.6 ? 35 35 181 268 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-126 ? ac loading table 2-145 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 1.0 1.0 1.5 10 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 10 pf 25 gtl+ vtt table 2-146 ? 3.3 v gtl+ commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v, vref = 1.0 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.06 0.04 1.59 0.43 2.09 2.06 4.33 4.29 ns ?1 0.56 1.75 0.04 1.35 0.36 1.78 1.75 3.68 3.65 ns ?2 0.49 1.53 0.03 1.19 0.32 1.56 1.53 3.23 3.20 ns note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-205 2.5 v gtl+ gunning transceiver logic plus is a high-speed bus standard (jesd8-3). it provides a differential amplifier input buffer and an open-drain output buffer. the vcci pin should be connected to 2.5 v. timing characteristics table 2-147 ? minimum and maximum dc input and output levels 2.5 v gtl+ vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 33 ma ?0.3 vref ? 0.1 vref + 0.1 3.6 0.6 ? 33 33 124 169 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-127 ? ac loading table 2-148 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring po int* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 1.0 1.0 1.5 10 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 10 pf 25 gtl+ vtt table 2-149 ? 2.5 v gtl+ commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v, vref = 1.0 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.21 0.04 1.51 0.43 2.25 2.10 4.48 4.34 ns ?1 0.56 1.88 0.04 1.29 0.36 1.91 1.79 3.81 3.69 ns ?2 0.49 1.65 0.03 1.13 0.32 1.68 1.57 3.35 4.34 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-206 revision 4 hstl class i high-speed transceiver logic is a general-purpo se high-speed 1.5 v bus standard (eia/jesd8-6). fusion devices support class i. this provides a differ ential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-150 ? minimum and maximum dc input and output levels hstl class i vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 8 ma ?0.3 vref ? 0.1 vref + 0.1 3 .6 0.4 vcci ? 0.4 8 8 39 32 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recomme nded operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-128 ? ac loading table 2-151 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring po int* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 0.75 0.75 0.75 20 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. t est point 20 p f 50 hstl class i vtt table 2-152 ? hstl class i commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v, vref = 0.75 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 3.18 0.04 2.12 0.43 3.24 3.14 5.47 5.38 ns ?1 0.56 2.70 0.04 1.81 0.36 2.75 2.67 4.66 4.58 ns ?2 0.49 2.37 0.03 1.59 0.32 2.42 2.35 4.09 4.02 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-207 hstl class ii high-speed transceiver logic is a general-purpo se high-speed 1.5 v bus standard (eia/jesd8-6). fusion devices support class ii. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-153 ? minimum and maximum dc input and output levels hstl class ii vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 15 ma 3 ?0.3 vref ? 0.1 vref + 0.1 3.6 0.4 vcci ? 0.4 15 15 55 66 10 10 note: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. output drive strength is below jedec specification. figure 2-129 ? ac loading table 2-154 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.1 vref + 0.1 0.75 0.75 0.75 20 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 20 pf 25 hstl class ii vtt table 2-155 ? hstl class ii commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v, vref = 0.75 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 3.02 0.04 2.12 0.43 3.08 2.71 5.32 4.95 ns ?1 0.56 2.57 0.04 1.81 0.36 2.62 2.31 4.52 4.21 ns ?2 0.49 2.26 0.03 1.59 0.32 2.30 2.03 3.97 3.70 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-208 revision 4 sstl2 class i stub-speed terminated logic for 2.5 v memory bus standard (jesd8-9). fusion devices support class i. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-156 ? minimum and maximum dc input and output levels sstl2 class i vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 15 ma ?0.3 vref ? 0.2 vref + 0.2 3.6 0.54 vcci ? 0.62 15 15 87 83 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-130 ? ac loading table 2-157 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring po int* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.25 1.25 1.25 30 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 30 pf 50 25 sstl2 class i vtt table 2-158 ? sstl 2 class i commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v, vref = 1.25 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.13 0.04 1.33 0.43 2.17 1.85 4.40 4.08 ns ?1 0.56 1.81 0.04 1.14 0.36 1.84 1.57 3.74 3.47 ns ?2 0.49 1.59 0.03 1.00 0.32 1.62 1.38 3.29 3.05 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-209 sstl2 class ii stub-speed terminated logic for 2.5 v memory bus standard (jesd8-9). fusion devices support class ii. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-159 ? minimum and maximum dc input and output levels sstl2 class ii vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 18 ma ?0.3 vref ? 0.2 vref + 0.2 3.6 0.35 vcci ? 0.43 18 18 124 169 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-131 ? ac loading table 2-160 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.25 1.25 1.25 30 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 30 pf 25 25 sstl2 class ii vtt table 2-161 ? sstl 2 class ii commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v, vref = 1.25 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.17 0.04 1.33 0.43 2.21 1.77 4.44 4.01 ns ?1 0.56 1.84 0.04 1.14 0.36 1.88 1.51 3.78 3.41 ns ?2 0.49 1.62 0.03 1.00 0.32 1.65 1.32 3.32 2.99 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-210 revision 4 sstl3 class i stub-speed terminated logic for 3.3 v memory bus standard (jesd8-8). fusion devices support class i. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-162 ? minimum and maximum dc input and output levels sstl3 class i vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 14 ma ?0.3 vref ? 0.2 vref + 0.2 3.6 0.7 vcci ? 1.1 14 14 54 51 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-132 ? ac loading table 2-163 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring po int* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.5 1.5 1.485 30 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 30 pf 50 25 sstl3 class i vtt table 2-164 ? sstl3 class i commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v, vref = 1.5 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.31 0.04 1.25 0.43 2.35 1.84 4.59 4.07 ns ?1 0.56 1.96 0.04 1.06 0.36 2.00 1.56 3.90 3.46 ns ?2 0.49 1.72 0.03 0.93 0.32 1.75 1.37 3.42 3.04 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-211 sstl3 class ii stub-speed terminated logic for 3.3 v memory bus standard (jesd8-8). fusion devices support class ii. this provides a differential amplifier input buffer and a push-pull output buffer. timing characteristics table 2-165 ? minimum and maximum dc input and output levels sstl3 class ii vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 21 ma ?0.3 vref ? 0.2 vref + 0. 2 3.6 0.5 vcci ? 0.9 21 21 109 103 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. figure 2-133 ? ac loading table 2-166 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring po int* (v) vref (typ.) (v) vtt (typ.) (v) c load (pf) vref ? 0.2 vref + 0.2 1.5 1.5 1.485 30 note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. test point 30 pf 25 25 sstl3 class ii vtt table 2-167 ? sstl3- class ii commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v, vref = 1.5 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units std. 0.66 2.07 0.04 1.25 0.43 2.10 1.67 4.34 3.91 ns ?1 0.56 1.76 0.04 1.06 0.36 1.79 1.42 3.69 3.32 ns ?2 0.49 1.54 0.03 0.93 0.32 1.57 1.25 3.24 2.92 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-212 revision 4 differential i/o characteristics configuration of the i/o modules as a differential pair is handled by the microsemi designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjuncti on with the embedded input r egister (inreg), output register (outreg), enable register (enreg), an d double data rate (ddr). however, there is no support for bidirectional i/os or tristates with these standards. lvds low-voltage differential signal (ansi/tia/eia-644) is a high-speed differential i/o standard. it requires that one data bit be carried through two signal lines , so two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitte r and receiver is shown in an example in figure 2-134 . the building bl ocks of the lvds transmitter?receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resi stor at the receiver end. the values for the three driver resistors are different from those used in the lvpecl implemen tation because the output standard specifications are different. figure 2-134 ? lvds circuit diagram and board-level implementation table 2-168 ? minimum and maximum dc input and output levels dc parameter description min. typ. max. units vcci supply voltage 2.375 2.5 2.625 v vol output low voltage 0.9 1.075 1.25 v voh input high voltage 1.25 1.425 1.6 v iol 1 output low voltage 0.65 0.91 1.16 ma ioh 1 output high voltage 0.65 0.91 1.16 ma vi input voltage 0 2.925 v iil 2,3 input low voltage 10 ? a iih 2,4 input high voltage 10 ? a vodiff differential output voltage 250 350 450 mv vocm output common mode voltage 1.125 1.25 1.375 v vicm input common mode voltage 0.05 1.25 2.35 v vidiff input differential voltage 100 350 mv notes: 1. iol/ioh defined by vodiff/(resistor network) 2. currents are measured at 85c junction temperature. 3. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 4. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 140 ? 100 ? zo = 50 ? zo = 50 ? 165 ? 165 ? + ? p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12
fusion family of mixed signal fpgas revision 4 2-213 timing characteristics blvds/m-lvds bus lvds (blvds) and multipoint lvds (m-lvds) specifications extend the existing lvds standard to high-performance multipoint bus applications. multidro p and multipoint bus configurations can contain any combination of drivers, receiv ers, and transceivers. microsemi lv ds drivers provide the higher drive current required by blvds and m-lvds to accommodate the loading. the driver requires series terminations for better signal quality and to control voltage swing. termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. thes e configurations can be implemented using tribuf_lvds and bibuf_lvds macros along with appropriate terminations. multipoint designs using microsemi lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sample application is given in figure 2-135 . the input and output buffer delays are available in the lvds section in table 2-171 . example: for a bus consisting of 20 equidistant lo ads, the following terminations provide the required differential voltage, in worst-case industrial operating conditions at the farthest receiver: r s =60 ? and r t =70 ? , given z 0 =50 ? (2") and z stub =50 ? (~1.5"). table 2-169 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ.) (v) 1.075 1.325 cross point ? note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. table 2-170 ? lvds commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v applicable to pro i/os speed grade t dout t dp t din t py units std. 0.66 2.10 0.04 1.82 ns ?1 0.56 1.79 0.04 1.55 ns ?2 0.49 1.57 0.03 1.36 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 . figure 2-135 ? blvds/m-lvds multipoint application using lvds i/o buffers ... r t r t bibuf_lvds r + - t + - r + - t + - d + - en en en en en receiver transceiver receiver transceiver driver r s r s r s r s r s r s r s r s r s r s z stub z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0
device architecture 2-214 revision 4 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differ ential i/o standard. it requires that one data bit be carried through two signal lines . like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitte r and receiver is shown in an example in figure 2-136 . the building blocks of t he lvpecl transmitter?receiver are one tr ansmitter macro, one receiver macro, three board resistors at the transmitter end, and one resi stor at the receiver end. the values for the three driver resistors are different from those used in the lvds implementation be cause the output standard specifications are different. timing characteristics figure 2-136 ? lvpecl circuit diag ram and board-leve l implementation table 2-171 ? minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units vcci supply voltage 3.0 3.3 3.6 v vol output low voltage 0.96 1.27 1.06 1.43 1.30 1.57 v voh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v vil, vih input low, input high voltages 0 3.6 0 3.6 0 3.6 v vodiff differential output voltage 0.625 0.97 0.625 0.97 0.625 0.97 v vocm output common mode voltage 1.762 1.98 1.762 1.98 1.762 1.98 v vicm input common mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v vidiff input differential voltage 300 300 300 mv table 2-172 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ.) (v) 1.64 1.94 cross point ? note: *measuring point = vtrip. see table 2-90 on page 2-169 for a complete table of trip points. 187 w 100 ? zo = 50 ? zo = 50 ? 100 ? 100 ? + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12 table 2-173 ? lvpecl commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v applicable to pro i/os speed grade t dout t dp t din t py units std. 0.66 2.14 0.04 1.63 ns ?1 0.56 1.82 0.04 1.39 ns ?2 0.49 1.60 0.03 1.22 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-215 i/o register specifications fully registered i/o buffers with synchronous enable and asynchronous preset figure 2-137 ? timing model of registered i/o buffers with synchronous enable and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive edge triggered data output register and enable output register with: active high enable active high preset postive edge triggered pad out clk enable preset data_out data x x x x x x x x x x x x x x eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
device architecture 2-216 revision 4 table 2-174 ? parameter definitions and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of the output data register l,dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the ou tput enable register j, h t oesue enable setup time for the ou tput enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time for the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of the input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a note: *see figure 2-137 on page 2-215 for more information.
fusion family of mixed signal fpgas revision 4 2-217 fully registered i/o buffers with synchronous enable and asynchronous clear figure 2-138 ? timing model of the registered i/o buffers wi th synchronous enable and asynchronous clear core array data input i/o register with active high enable active high clear positive edge triggered data output register and enable output register with active high enable active high clear positive edge triggered enable clk pad out clk enable clr data_out data y aa eout dout dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf
device architecture 2-218 revision 4 table 2-175 ? parameter definitions and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the output enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the output enable register kk, hh t oehe enable hold time for the output enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time for the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa note: *see figure 2-138 on page 2-217 for more information.
fusion family of mixed signal fpgas revision 4 2-219 input register timing characteristics figure 2-139 ? input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-176 ? input data register propagation delays commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t iclkq clock-to-q of the input da ta register 0.24 0.27 0.32 ns t isud data setup time for the input data register 0.26 0.30 0.35 ns t ihd data hold time for the input data register 0.00 0.00 0.00 ns t isue enable setup time for the input data register 0.37 0.42 0.50 ns t ihe enable hold time for the input data register 0.00 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the inpu t data register 0.45 0.52 0.61 ns t ipre2q asynchronous preset-to-q of the in put data register 0.45 0.52 0.61 ns t iremclr asynchronous clear removal time for the input data register 0.00 0.00 0.00 ns t irecclr asynchronous clear recovery time for the input data regi ster 0.22 0.25 0.30 ns t irempre asynchronous preset removal time for the input data register 0.00 0.00 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.22 0.25 0.30 ns t iwclr asynchronous clear minimum pulse width fo r the input data r egister 0.22 0.25 0.30 ns t iwpre asynchronous preset minimum pulse width fo r the input data r egister 0.22 0.25 0.30 ns t ickmpwh clock minimum pulse width high for the input data register 0.36 0.41 0.48 ns t ickmpwl clock minimum pulse width low for t he input data register 0.32 0.37 0.43 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-220 revision 4 output register timing characteristics figure 2-140 ? output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-177 ? output data register propagation delays commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t oclkq clock-to-q of the output data register 0.59 0.67 0.79 ns t osud data setup time for the output data register 0.31 0.36 0.42 ns t ohd data hold time for the output data register 0.00 0.00 0.00 ns t osue enable setup time for the output data register 0.44 0.50 0.59 ns t ohe enable hold time for the output data register 0.00 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the out put data register 0.80 0.91 1.07 ns t opre2q asynchronous preset-to-q of the ou tput data register 0.80 0.91 1.07 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 0.00 ns t orecclr asynchronous clear recovery time for t he output data regi ster 0.22 0.25 0.30 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.22 0.25 0.30 ns t owclr asynchronous clear minimum pulse width for the output data register 0.22 0.25 0.30 ns t owpre asynchronous preset minimum pu lse width for the output data register 0.22 0.25 0.30 ns t ockmpwh clock minimum pulse width high for the output data register 0.36 0.41 0.48 ns t ockmpwl clock minimum pulse width low for the output data register 0.32 0.37 0.43 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
fusion family of mixed signal fpgas revision 4 2-221 output enable register timing characteristics figure 2-141 ? output enable register timing diagram 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-178 ? output enable register propagation delays commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t oeclkq clock-to-q of the output enable register 0.44 0.51 0.59 ns t oesud data setup time for the output enable register 0.31 0.36 0.42 ns t oehd data hold time for the output enable register 0.00 0.00 0.00 ns t oesue enable setup time for the output enable register 0.44 0.50 0.58 ns t oehe enable hold time for the output enable register 0.00 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the out put enable regist er 0.67 0.76 0.89 ns t oepre2q asynchronous preset-to-q of the ou tput enable regist er 0.67 0.76 0.89 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 0.00 0.00 ns t oerecclr asynchronous clear recovery time for t he output enable regi ster 0.22 0.25 0.30 ns t oerempre asynchronous preset removal time for th e output enable register 0.00 0.00 0.00 ns t oerecpre asynchronous preset recovery time for the output enable r egister 0.22 0.25 0.30 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.22 0.25 0.30 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.22 0.25 0.30 ns t oeckmpwh clock minimum pulse width high for the output enable regi ster 0.36 0.41 0.48 ns t oeckmpwl clock minimum pulse width low for the output enable regi ster 0.32 0.37 0.43 ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-222 revision 4 ddr module sp ecifications input ddr module figure 2-142 ? input ddr timing model table 2-179 ? parameter definitions parameter name parameter defini tion measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
fusion family of mixed signal fpgas revision 4 2-223 timing characteristics figure 2-143 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-180 ? input ddr propagation delays commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.39 0.44 0.52 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.27 0.31 0.37 ns t ddrisud data setup for input ddr 0.28 0.32 0.38 ns t ddrihd data hold for input ddr 0.00 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.57 0.65 0.76 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.46 0.53 0.62 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.22 0.25 0.30 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.22 0.25 0.30 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.36 0.41 0.48 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.32 0.37 0.43 ns f ddrimax maximum frequency for input ddr 1404 1232 1048 mhz note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-224 revision 4 output ddr figure 2-144 ? output ddr timing model table 2-181 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out ff1 0 1 a b d e c c b outbuf data_r (from core)
fusion family of mixed signal fpgas revision 4 2-225 timing characteristics figure 2-145 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddrosud1 t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-182 ? output ddr propagation delays commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 0.70 0.80 0.94 ns t ddrosud1 data_f data setup for output ddr 0.38 0.43 0.51 ns t ddrosud2 data_r data setup for output ddr 0.38 0.43 0.51 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out fo r output ddr 0.80 0.91 1.07 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.22 0.25 0.30 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.22 0.25 0.30 ns t ddrockmpwh clock minimum pulse width high fo r the output ddr 0.36 0.41 0.48 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.32 0.37 0.43 ns f ddomax maximum frequency for the output ddr 1404 1232 1048 mhz note: for the derating values at specific junction te mperature and voltage supply levels, refer to table 3-7 on page 3-9 .
device architecture 2-226 revision 4 pin descriptions supply pins gnd ground ground supply voltage to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. within the package, the gndq plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. this minimizes the noise transfer within the package and improves input signal in tegrity. gndq needs to always be connected on the board to gnd. note: in fg256, fg484, and fg 676 packages, gndq and gnd pins are connected within the package and are labeled as gnd pins in the respective package pin assignment tables. adcgndref analog reference ground analog ground reference used by the adc. this pad should be connected to a quiet analog ground. gnda ground (analog) quiet ground supply voltage to the analog block of fusion devices. the use of a separate analog ground helps isolate the analog functiona lity of the fusion device from any digital switching noise. a 0.2 v maximum differential volt age between gnd a nd gnda/gndq should apply to system implementation. gndaq ground (analog quiet) quiet ground supply voltage to the analog i/o of fu sion devices. the use of a separate analog ground helps isolate the analog functiona lity of the fusion device from any digital switching noise. a 0.2 v maximum differential voltage between gnd and g nda/gndq should apply to system implementation. note: in fg256, fg484, and fg676 packages, g ndaq and gnda pins are connected within the package and are labeled as gnda pins in the respective package pin assignment tables. gndnvm flash memory ground ground supply used by the fusion device's flash memory block module(s). gndosc oscillator ground ground supply for both integrated rc o scillator and crystal oscillator circuit. vcc15a analog power supply (1.5 v) 1.5 v clean analog power supply input for use by the 1.5 v portion of the analog circuitry. vcc33a analog power supply (3.3 v) 3.3 v clean analog power supply input for use by the 3.3 v portion of the analog circuitry. vcc33n negative 3.3 v output this is the ?3.3 v output from the voltage converter. a 2.2 f capacitor must be connected from this pin to ground. vcc33pmp analog power supply (3.3 v) 3.3 v clean analog power supply input for use by th e analog charge pump. to avoid high current draw, vcc33pmp should be powered up simultaneously with or after vcc33a. vccnvm flash memory block power supply (1.5 v) 1.5 v power supply input used by the fusion device's flash memory block module(s). to avoid high current draw, vcc should be powered up before or simultaneously with vccnvm.
fusion family of mixed signal fpgas revision 4 2-227 vccosc oscillator power supply (3.3 v) power supply for both integrated rc oscillator and crystal oscillator circuit. the internal 100 mhz oscillator, powered by the vccosc pin, is needed for device programming, operation of the vddn33 pump, and envm operation. vccosc is off only when vcca is off. vccosc must be powered whenever the fusion device needs to function. vcc core supply voltage supply voltage to the fpga core, nominally 1.5 v. vcc is also required for powering the jtag state machine, in addition to vjtag. even when a fusion device is in bypass mode in a jtag chain of interconnected devices, both vcc and vjtag must remain powered to allow jtag signals to pass through the fusion device. vccibx i/o supply voltage supply voltage to the bank's i/o output buffers and i/o logic. b x is the i/o bank number. there are either four (afs090 and afs250) or five (afs600 and afs1500) i/o banks on the fusion devices plus a dedicated vjtag bank. each bank can have a separate vcci connection. all i/os in a bank will run off the same vccibx supply. vcci can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vcci pins tied to gnd. vccpla/b pll supply voltage supply voltage to analog pll, nominally 1.5 v, wher e a and b refer to the pll. afs090 and afs250 each have a single pll. the afs600 and afs1500 devices each have two plls. microsemi recommends tying vccplx to vcc and using proper filt ering circuits to decouple vcc noise from pll. if unused, vccpla/b should be tied to gnd. vcompla/b ground for west and east pll vcompla is the ground of the west pll (ccc locati on f) and vcomplb is the ground of the east pll (ccc location c). vjtag jtag supply voltage fusion devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isolating t he jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned to be used, the vjtag pin t ogether with the trst pin could be tied to gnd. it should be noted that vcc is required to be powered fo r jtag operation; vjtag alone is insufficient. if a fusion device is in a jtag chain of interconnected boards and it is desired to power down the board containing the fusion device, this may be done prov ided both vjtag and vcc to the fusion part remain powered; otherwise, jtag signals wi ll not be able to transition the fusion device, even in bypass mode. vpump programming supply voltage fusion devices support single-voltage isp programming of the configuration flash and flashrom. for programming, vpump should be in the 3.3 v +/-5% range. during normal device operation, vpump can be left floating or can be tied to any voltage between 0 v and 3.6 v. when the vpump pin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacitors (both rated at 16 v) are to be connected in parallel across vpump and gnd, and positioned as close to the fpga pins as possible.
device architecture 2-228 revision 4 user-defined supply pins vref i/o voltage reference reference voltage for i/o minibanks. both afs600 and afs1500 (north bank only) support microsemi pro i/o. these i/o banks support voltage reference st andard i/o. the vref pins are configured by the user from regular i/os, and any i/o in a bank, e xcept jtag i/os, can be designated as the voltage reference i/o. only certain i/o standards require a voltage reference?hstl (i) and (ii), sstl2 (i) and (ii), sstl3 (i) and (ii), and gtl/gtl+. one vref pin can support the number of i/os available in its minibank. varef analog reference voltage the fusion device can be configured to generate a 2. 56 v internal reference voltage that can be used by the adc. while using the internal reference, the reference voltage is output on the varef pin for use as a system reference. if a different reference voltage is required, it can be suppl ied by an external source and applied to this pin. the valid range of values that can be supplied to the adc is 1.0 v to 3.3 v. when varef is internally generated by the fusion device, a bypass capacitor must be connected from this pin to ground. the value of the bypass capacitor should be between 3.3 f and 22 f, which is based on the needs of the individual designs. the choice of the capacitor value has an impact on the settling time it takes the varef signal to reach the required specificat ion of 2.56 v to initiate valid conversions by the adc. if the lower capacitor value is chosen, the sett ling time required for varef to achieve 2.56 v will be shorter than when selecting the larger capacitor value. the above range of capacitor values supports the accuracy specification of the adc, which is deta iled in the datasheet. designers choosing the smaller capacitor value will not obtain as much margin in t he accuracy as that achieved with a larger capacitor value. depending on the capacitor value selected in the analog system builder, a tool in libero soc, an automatic delay circuit will be generated using logic t iles available within the fpga to ensure that varef has achieved the 2.56 v value. microsemi recommends customers use 10 f as the value of the bypass capacitor. designers choosing to use an external varef need to ensure that a stable and clean varef source is supplied to the varef pin before initia ting conversions by the adc. designers should also make sure that the adcreset signal is dea sserted before initiating valid conversions. 2 if the user connects varef to external 3.3 v on th eir board, the internal varef driving opamp tries to bring the pin down to the nominal 2.56 v until the device is programmed and up/functional. under this scenario, it is recommended to connect an external 3.3 v supply through a ~1 kohm resistor to limit current, along with placing a 10-100nf capacitor between varef and gnda. user pins i/o user input/output the i/o pin functions as an input, output, tristate, or bi directional buffer. input and output signal levels are compatible with the i/o standard selected. unused i/o pins are configured as inputs with pull-up resistors. during programming, i/os become tristated and weakly pulled up to vcci. with the vcci and vcc supplies continuously powered up, when the device tr ansitions from programming to operating mode, the i/os get instantly configured to the desired user configuration. unused i/os are configured as follows: ? output buffer is disabled (with tristate value of high impedance) ? input buffer is disabled (with tristate value of high impedance) ? weak pull-up is programmed a xy analog input/output analog i/o pin, where x is the analog pad type (c = current pa d, g = gate driver pad, t = temperature pad, v = voltage pad) and y is the analog quad number (0 to 9). there is a minimum 1 m ? to ground on av, ac, and at. this pin can be left floating when it is unused. 2. the adc is functional with an external reference down to 1v, however to meet the performance parameters highlighted in the datasheet refer to the varef specification in table 3-2 on page 3-3 .
fusion family of mixed signal fpgas revision 4 2-229 atrtn x temperature monitor return at returns are the returns for the temperature sensors. the cathode terminal of the external diodes should be connected to these pins. there is one analog return pin for every two analog quads. the x in the atrtn x designator indicates the quad pairing ( x = 0 for aq1 and aq2, x = 1 for aq2 and aq3, ..., x = 4 for aq8 and aq9). the signals that driv e these pins are called out as atreturn xy in the software (where x and y refer to the quads that share the return signal). atrtn is internally connected to ground. it can be left floating when it is unused. the maximu m capacitance allowed across the at pins is 500 pf. gl globals gl i/os have access to certain clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the global i/os can be used as pro i/os since they have identical capabilities. unused gl pins are configured as inputs with pull-up resistors. see more detailed descriptions of global i/o connectivity in the "clock conditioning circuits" section on page 2-23 . refer to the "user i/o naming convention" section on page 2-161 for a description of naming of global pins. jtag pins fusion devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). vcc must also be powered for the jtag state machine to operate, even if the device is in bypass mode; vjtag alone is insufficient. both vjtag and vcc to the fusion part must be supplied to allow jtag signals to transition the fusion device. isolating the jtag power supply in a separate i/o ban k gives greater flexibility with supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned to be used, the vjtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and uj tag. the tck pin does not have an internal pull- up/-down resistor. if jtag is not used, microsemi recommends tying off tck to gnd or vjtag through a resistor placed close to the fpga pin. this prev ents jtag operation in case tms enters an undesired state. note that to operate at all vjtag voltages, 500 ? to 1 k ? will satisfy the requirements. refer to table 2-183 for more information. tdi test data input serial input for jtag boundary scan, isp, and ujtag us age. there is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jtag boundary scan, isp, and ujtag usage. table 2-183 ? recommended tie-off values for the tck and trst pins vjtag tie-off resistance 2, 3 vjtag at 3.3 v 200 ? to 1 k ? vjtag at 2.5 v 200 ? to 1 k ? vjtag at 1.8 v 500 ? to 1 k ? vjtag at 1.5 v 500 ? to 1 k ? notes: 1. equivalent parallel resistance if more than one device is on jtag chain. 2. the tck pin can be pulled up/down. 3. the trst pin can only be pulled down.
device architecture 2-230 revision 4 tms test mode select the tms pin controls the use of the ieee1532 boundary scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the trst pin. if jtag is not used, an external pull- down resistor could be included to ensure the tap is held in reset mode. the resistor values must be chosen from table 2-183 and must satisfy the parallel resistance value requirement. the values in table 2-183 correspond to the resistor recommended when a single device is used and to the equivalent parallel resistor when multiple devices are connected via a jtag chain. in critical applications, an upset in the jtag circuit could allow entering an undesired jtag state. in such cases, microsemi recommends tying off trst to gnd through a resistor placed close to the fpga pin. note that to operate at all vjtag voltages, 500 ? to 1 k ? will satisfy the requirements. special function pins nc no connect this pin is not connected to circuitry within the devic e. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. dc don't connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. ncap negative capacitor negative capacitor is where the negative termi nal of the charge pump capacitor is connected. a capacitor, with a 2.2 f recommended value, is required to connect between pcap and ncap. pcap positive capacitor positive capacitor is where the positive terminal of the char ge pump capacitor is connected. a capacitor, with a 2.2 f recommended value, is required to connect between pcap and ncap. pub push button push button is the connection for the external momentar y switch used to turn on the 1.5 v voltage regulator and can be floating if not used. ptbase pass transistor base pass transistor base is the control signal of the voltage regulator. this pin should be connected to the base of the external pass transistor used with the 1. 5 v internal voltage regulator and can be floating if not used. ptem pass transistor emitter pass transistor emitter is the feedback input of the voltage regulator. this pin should be connected to the emitter of the external pass transistor used with the 1.5 v internal voltage regulator and can be floating if not used. xtal1 crystal oscillator circuit input input to crystal oscillator circuit. pin for connec ting external crystal, ceramic resonator, rc network, or external clock input. when using an external crystal or ceramic oscillator, external capacitors are also recommended (please refer to the crystal oscillato r manufacturer for proper capacitor value). if using external rc network or clock input, xtal1 should be used and xtal2 left unconnected. in the case where the crystal oscillator block is not used, the xtal1 pin should be connected to gnd and the xtal2 pin should be left floating.
fusion family of mixed signal fpgas revision 4 2-231 xtal2 crystal oscillator circuit input input to crystal oscillator circuit. pin for connec ting external crystal, ceramic resonator, rc network, or external clock input. when using an external crystal or ceramic oscillator, external capacitors are also recommended (please refer to the crystal oscillato r manufacturer for proper capacitor value). if using external rc network or clock input, xtal1 should be used and xtal2 left unconnected. in the case where the crystal oscillator block is not used, the xtal1 pin should be connected to gnd and the xtal2 pin should be left floating. security fusion devices have a built -in 128-bit aes decryption core. the decr yption core facilitat es highly secure, in-system programming of the fpga core array f abric and the flashrom. the flashrom and the fpga core fabric can be programmed independently from each other, allowing the flashrom to be updated without the need for change to the fpga core fabric. th e aes master key is stored in on-chip nonvolatile memory (flash). the aes master key can be preloade d into parts in a security-protected programming environment (such as the microsemi in-house pr ogramming center), and then "blank" parts can be shipped to an untrusted programming or manufactur ing center for final personalization with an aes- encrypted bitstream. late stage product changes or personalization can be implemented easily and with high level security by simply sending a stapl file with aes-encrypted data. hi ghly secure remote field updates over public networks (such as the inter net) are possible by sending and programming a stapl file with aes-encrypted data. for mo re information, refer to the fusion security application note. 128-bit aes decryption the 128-bit aes standard (fips-197) block cipher is the national institute of standards and technology (nist) replacement for des (data encryption standard fips46-2). aes has been designed to protect sensitive government information well into the 21st century. it replaces the aging des, which nist adopted in 1977 as a federal information processi ng standard used by federal agencies to protect sensitive, unclassified information. the 128-bit aes standard has 3.4 10 38 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit aes cipher text using exhaustive techniques. keys are stored (protect ed with security) in fusion devices in nonvolatile flash memory. all programming files sent to the de vice can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. all programming verification is performed on-chip, ensuring that the contents of fusion devices remain as secure as possible. aes decryption can also be used on the 1,024-bit fl ashrom to allow for remote updates of the flashrom contents. this allows fo r easy support of subscription mode l products and protects them with measures designed to provide the highest level of security available. see the application note fusion security for more details. aes for flash memory aes decryption can also be used on the flash memory bl ocks. this provides the best available security during update of the flash memory blocks. during runt ime, the encrypted data can be clocked in via the jtag interface. the data can be passed through th e internal aes decryption engine, and the decrypted data can then be stored in the flash memory block. programming programming can be performed using various programming tools, such as silicon sculptor ii (bp micro systems) or flashpro3 (microsemi). the user can generate stp programming files from the designer software and can use these files to program a device. fusion devices can be programmed in-system. duri ng programming, vccosc is needed in order to power the internal 100 mhz oscillator. this oscillator is used as a source for the 20 mhz oscillator that is used to drive the charge pump for programming.
device architecture 2-232 revision 4 isp fusion devices support ieee 1532 isp via jtag and require a single vpump voltage of 3.3 v during programming. in addition, programming via a microcontro ller in a target system can be achieved. refer to the standard or the "in-system programming (isp) of microsemi's low po wer flash devices using flashpro4/3/3x" chapter of the fusion fpga fabric user?s guide for more details. jtag ieee 1532 programming with ieee 1532 fusion devices support the jtag-based ieee1532 stand ard for isp. as part of this support, when a fusion device is in an unprogrammed state, all user i/o pins are disabled. this is achieved by keeping the global io_en signal deactivated, which also has the effect of disabling the input buffers. consequently, the sample instruction will have no effect while the fusion device is in this unprogrammed state?different behav ior from that of the proasic plus ? device family. this is done because sample is defined in the ieee1532 specific ation as a noninvasive instruction. if the input buffers were to be enabled by sample temporarily turning on the i/os, then it would not truly be a noninvasive instruction. refer to the standard or t he "in-system programming (isp) of microsemi's low power flash devices using flashpro4/3/3x" chapter of the fusion fpga fabric user?s guide for more details. boundary scan fusion devices are compatible with ieee standard 1149.1, which defin es a hardware architecture and the set of mechanisms for boundary scan testing. the basic fusion boundary scan logic circuit is composed of the test access port (t ap) controller, test data regist ers, and instruction register ( figure 2- 146 on page 2-233 ). this circuit supports all mandato ry ieee 1149.1 instructions (extest, sample/preload, and bypass) and th e optional idcode instruction ( table 2-185 on page 2-233 ). each test section is accessed through the tap, whic h has five associated pins: tck (test clock input), tdi, tdo (test data input and output ), tms (test mode selector), and trst (test reset input). tms, tdi, and trst are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundary scan test usage. refer to the "jtag pins" section on page 2-229 for pull-up/-down recommendations for tdo and tck pins. the tap controller is a 4-bit state machine (16 states) that operates as shown in figure 2-146 on page 2-233 . the 1s and 0s represent the values that must be present on tms at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. the tap controller receives two control inputs (tms and tck) and generates control and clock signals for the rest of the test logic architecture. on pow er-up, the tap controller enters the test-logic-reset state. to guarantee a reset of the controller from any of the possible states, tms must remain high for five tck cycles. the trst pin can also be used to asynchronously place the tap controller in the test- logic-reset state. fusion devices support three types of test data regi sters: bypass, device id entification, and boundary scan. the bypass register is sele cted when no other register needs to be accessed in a device. this speeds up test data transfer to other devices in a te st data path. the 32-bit device identific ation register is a shift register with four fields (lsb, id number, part number, and version). the boundary scan register observes and controls the state of each i/o pin. ea ch i/o cell has three boundary scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. the serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register chain, which starts at the td i pin and ends at the tdo pin. the parallel ports are table 2-184 ? trst and tck pull-down recommendations vjtag tie-off resistance* vjtag at 3.3 v 200 ? to 1 k ? vjtag at 2.5 v 200 ? to 1 k ? vjtag at 1.8 v 500 ? to 1 k ? vjtag at 1.5 v 500 ? to 1 k ? note: *equivalent parallel resistance if more than one device is on jtag chain.
fusion family of mixed signal fpgas revision 4 2-233 connected to the internal core logic i/o tile and th e input, output, and control ports of an i/o buffer to capture and load data into the register to control or observe the logic state of each i/o. figure 2-146 ? boundary scan chain in fusion table 2-185 ? boundary scan opcodes hex opcode extest 00 highz 07 usercode 0e sample/preload 01 idcode 0f clamp 05 bypass ff device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers
ieee 1532 characteristics jtag timing delays do not include jtag i/os. to obtai n complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/os" section on page 2-135 for more details. timing characteristics table 2-186 ? jtag 1532 commercial temperature range conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time 0.50 0.57 0.67 ns t dihd test data input hold time 1.00 1.13 1.33 ns t tmssu test mode select setup time 0.50 0.57 0.67 ns t tmdhd test mode select hold time 1.00 1.13 1.33 ns t tck2q clock to q (data out) 6.00 6.80 8.00 ns t rstb2q reset to q (data out) 20.00 22.67 26.67 ns f tckmax tck maximum frequency 25.00 22.00 19.00 mhz t trstrem resetb removal time 0.00 0.00 0.00 ns t trstrec resetb recovery time 0.20 0.23 0.27 ns t trstmpw resetb minimum pulse tbd tbd tbd ns note: for the derating values at specific junction temperature and voltage supply levels, refer to table 3-7 on page 3-9 .
revision 4 3-1 3 ? dc and power characteristics general specifications operating conditions stresses beyond those listed in ta b l e 3 - 1 may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. devices should not be operated outside the recommended operating ranges specified in table 3-2 on page 3-3 . table 3-1 ? absolute maximum ratings symbol parameter commercial industrial units vcc dc core supply voltage ?0.3 to 1.65 ?0.3 to 1.65 v vjtag jtag dc voltage ?0.3 to 3.75 ?0.3 to 3.75 v vpump programming voltage ?0.3 to 3.75 ?0.3 to 3.75 v vccpll analog power supply (pll) ?0.3 to 1.65 ?0.3 to 1.65 v vcci dc i/o output buffer supply voltage ?0.3 to 3.75 ?0.3 to 3.75 v vi i/o input voltage 1 ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (vcci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-insertion mode is disabled) v vcc33a +3.3 v power supply ?0.3 to 3.75 2 ?0.3 to 3.75 2 v vcc33pmp +3.3 v power supply ?0.3 to 3.75 2 ?0.3 to 3.75 2 v varef voltage reference for adc ?0.3 to 3.75 ?0.3 to 3.75 v vcc15a digital power supply for the analog system ?0.3 to 1.65 ?0.3 to 1.65 v vccnvm embedded flash power supply ?0.3 to 1.65 ?0.3 to 1.65 v vccosc oscillator power supply ?0.3 to 3.75 ?0.3 to 3.75 v notes: 1. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 3-4 on page 3-4 . 2. analog data not valid beyond 3.65 v. 3. the high current mode has a maximum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 4. for flash programming and retention maximum limits, refer to table 3-5 on page 3-5 . for recommended operating limits refer to table 3-2 on page 3-3 .
dc and power characteristics 3-2 revision 4 av, ac unpowered, adc reset asserted or unconfigured ?11.0 to 12.6 ?11.0 to 12.0 v analog input (+16 v to +2 v prescaler range) ?0.4 to 12.6 ?0.4 to 12.0 v analog input (+1 v to +0.125 v prescaler range) ?0.4 to 3.75 ?0.4 to 3.75 v analog input (?16 v to ?2 v prescaler range) ?11.0 to 0.4 ?11.0 to 0.4 v analog input (?1 v to ?0.125 v prescaler range) ?3.75 to 0.4 ?3.75 to 0.4 v analog input (direct input to adc) ?0.4 to 3.75 ?0.4 to 3.75 v digital input ?0.4 to 12.6 ?0.4 to 12.0 v ag unpowered, adc reset asserted or unconfigured ?11.0 to 12.6 ?11.0 to 12.0 v low current mode (1 a, 3 a, 10 a, 30 a) ?0.4 to 12.6 ?0.4 to 12.0 v low current mode (?1 a, ?3 a, ?10 a, ?30 a) ?11.0 to 0.4 ?11.0 to 0.4 v high current mode 3 ?11.0 to 12.6 ?11.0 to 12.0 v at unpowered, adc reset asserted or unconfigured ?0.4 to 16.0 ?0.4 to 15.0 v analog input (+16 v, 4 v prescaler range) ?0.4 to 16.0 ?0.4 to 15.0 v analog input (direct input to adc) ?0.4 to 3.75 ?0.4 to 3.75 v digital input ?0.4 to 16.0 ?0.4 to 15.0 v t stg 4 storage temperature ?65 to +150 c t j 4 junction temperature +125 c table 3-1 ? absolute maximum ra tings (continued) symbol parameter commercial industrial units notes: 1. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 3-4 on page 3-4 . 2. analog data not valid beyond 3.65 v. 3. the high current mode has a maximum power limit of 20 mw. appropriate current limit resistors must be used, based on voltage on the pad. 4. for flash programming and retention maximum limits, refer to table 3-5 on page 3-5 . for recommended operating limits refer to table 3-2 on page 3-3 .
fusion family of mixed signal fpgas revision 4 3-3 table 3-2 ? recommended operating conditions 1 symbol parameter 2 commercial industrial units t j junction temperature 0 to +85 ?40 to +100 c vcc 1.5 v dc core supply voltage 1.425 to 1.575 1.425 to 1.575 v vjtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v vpump programming voltage programming mode 3 3.15 to 3.45 3.15 to 3.45 v operation 4 0 to 3.6 0 to 3.6 v vccpll analog power supply (pll) 1.425 to 1.575 1.425 to 1.575 v vcci 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds differential i/o 2. 375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3.0 to 3.6 3.0 to 3.6 v vcc33a +3.3 v power supply 2.97 to 3.63 2.97 to 3.63 v vcc33pmp +3.3 v power supply 2.97 to 3.63 2.97 to 3.63 v varef voltage reference for adc 2.527 to 2.593 2.527 to 2.593 v vcc15a 5 digital power supply for the analog system 1.425 to 1.575 1.425 to 1.575 v vccnvm embedded flash power supply 1 .425 to 1.575 1.425 to 1.575 v vccosc oscillator power supply 2 .97 to 3.63 2.97 to 3.63 v av, ac 6 unpowered, adc reset asserted or uncon figured ?10.5 to 12.0 ?10.5 to 11.6 v analog input (+16 v to +2 v prescale r range) ?0.3 to 12.0 ?0.3 to 11.6 v analog input (+1 v to + 0.125 v pre scaler range) ?0.3 to 3.6 ?0.3 to 3.6 v analog input (?16 v to ?2 v prescaler range) ?10.5 to 0.3 ?10.5 to 0.3 v analog input (?1 v to ?0.125 v prescaler range) ?3.6 to 0.3 ?3.6 to 0.3 v analog input (direct input to adc) ?0.3 to 3.6 ?0.3 to 3.6 v digital input ?0.3 to 12.0 ?0.3 to 11.6 v ag 6 unpowered, adc reset asserted or uncon figured ?10.5 to 12.0 ?10.5 to 11.6 v low current mode (1 a, 3 a, 10 a, 30 a) ?0.3 to 12.0 ?0.3 to 11.6 v low current mode (?1 a, ?3 a, ?10 a , ?30 a) ?10.5 to 0.3 ?10.5 to 0.3 v high current mode 7 ?10.5 to 12.0 ?10.5 to 11.6 v at 6 unpowered, adc reset asserted or unconfigured ?0.3 to 15.5 ?0.3 to 14.5 v analog input (+16 v, +4 v prescaler range) ?0.3 to 15.5 ?0.3 to 14.5 v analog input (direct input to adc) ?0.3 to 3.6 ?0.3 to 3.6 v digital input ?0.3 to 15.5 ?0.3 to 14.5 v notes: 1. the ranges given here are for power supplies only. the recommended input voltage ranges specific to each i/o standard are given in table 2-85 on page 2-160 . 2. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 3. the programming temperature range supported is t ambient = 0c to 85c. 4. vpump can be left floating during normal operation (not programming mode). 5. violating the v cc15a recommended voltage supply during an embedded flash program cycle can corrupt the page being programmed. 6. the input voltage may overshoot by up to 500 mv above the recommended maximum (150 mv in direct mode), provided the duration of the overshoot is less than 50% of the operating lifetime of the device. 7. the ag pad should also conform to the limits as specified in table 2-48 on page 2-117 .
dc and power characteristics 3-4 revision 4 table 3-3 ? input resistance of analog pads pads pad configuration prescaler range input resistance to ground av, ac analog input (direct input to adc) ? 2 k ? (typical) ? > 10 m ? analog input (positive prescaler) +16 v to +2 v 1 m ? (typical) +1 v to +0.125 v > 10 m ? analog input (negative prescaler) ?16 v to ?2 v 1 m ? (typical) ?1 v to ?0.125 v > 10 m ? digital input +16 v to +2 v 1 m ? (typical) current monitor +16 v to +2 v 1 m ? (typical) ?16 v to ?2 v 1 m ? (typical) at analog input (direct input to adc) ? 1 m ? (typical) analog input (positive prescaler) +16 v, +4 v 1 m ? (typical) digital input +16 v, +4 v 1 m ? (typical) temperature monitor +16 v, +4 v > 10 m ? table 3-4 ? overshoot and undershoot limits 1 vcci average vcci?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3.0 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at a junction temperature of 85c. 2. the duration is allowed at one cycle out of six clock cycle. if the overshoot/unde rshoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v.
fusion family of mixed signal fpgas revision 4 3-5 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is des igned into every fusion device. these circuits ensure easy transition from the powered off state to the powered up state of the device. the many different supplies can power up in any sequence with mi nimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 3-1 on page 3-6 . there are five regions to consider during power-up. fusion i/os are activated only if all of the following three conditions are met: 1. vcc and vcci are above the minimum specified trip points ( figure 3-1 ). 2. vcci > vcc ? 0.75 v (typical). 3. chip is in the operating mode. v cci trip point: ramping up: 0.6 v < trip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v v cc trip point: ramping up: 0.6 v < trip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v vcc and vcci ramp-up trip points are about 100 mv hi gher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tristated and weakly pulled up to vcci. ? jtag supply, pll power supplies, and charge pump vpump supply have no influence on i/o behavior. internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns delay from input buffer activation pll behavior at brownout condition microsemi recommends using monotonic power supplie s or voltage regulators to ensure proper power- up behavior. power ramp-up should be monotonic at least until vcc and vccplx exceed brownout activation levels. the v cc activation level is specified as 1.1 v worst-case (see figure 3-1 on page 3-6 for more details). when pll power supply voltage and/or vcc levels drop below the vcc brownout levels (0.75 v 0.25 v), the pll output lock signal goes low and/or the output clock is lost. table 3-5 ? fpga programming, storage, and operating limits product grade storage temperature element grade programming cycles retention commercial min. t j = 0c fpga/flashrom 500 20 years max. t j = 85c embedded flash < 1,000 20 years < 10,000 10 years < 15,000 5 years industrial min. t j = ?40c fpga/flashrom 500 20 years max. t j = 100c embedded flash < 1,000 20 years < 10,000 10 years < 15,000 5 years
dc and power characteristics 3-6 revision 4 figure 3-1 ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because vcci / vcc are below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v vcc vcc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil, voh vol, etc. region 4: i/o buffers are on. i/os are functional (except differential inputs) but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcc = vcci + vt vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification
fusion family of mixed signal fpgas revision 4 3-7 thermal characteristics introduction the temperature variable in the micr osemi designer software refers to the junction temperature, not the ambient, case, or board temperatures. this is an im portant distinction because dynamic and static power consumption will cause the chip's junction temperatur e to be higher than the ambient, case, or board temperatures. eq 1 through eq 3 give the relationship between thermal resistance, temperature gradient, and power. eq 1 eq 2 eq 3 where ? ja = junction-to-air thermal resistance ? jb = junction-to-board thermal resistance ? jc = junction-to-case thermal resistance t j = junction temperature t a = ambient temperature t b = board temperature (measured 1.0 mm away from the package edge) t c = case temperature p = total power dissipated by the device ? ja t j ? a ? p ------------------ = ? jb t j t b ? p ------------------ - = ? jc t j t c ? p ------------------- = table 3-6 ? package thermal resistance product ? ja ? jc ? jb units still air 1.0 m/s 2.5 m/s afs090-qn108 34.5 30.0 27.7 8.1 16.7 c/w afs090-qn180 33.3 27.6 25.7 9.2 21.2 c/w afs250-qn180 32.2 26.5 24.7 5.7 15.0 c/w afs250-pq208 42.1 38.4 37 20.5 36.3 c/w afs600-pq208 23.9 21. 3 20.48 6.1 16.5 c/w afs090-fg256 37.7 33.9 32.2 11.5 29.7 c/w afs250-fg256 33.7 30.0 28.3 9.3 24.8 c/w afs600-fg256 28.9 25.2 23.5 6.8 19.9 c/w afs1500-fg256 23.3 19.6 18.0 4.3 14.2 c/w afs600-fg484 21.8 18.2 16.7 7.7 16.8 c/w afs1500-fg484 21.6 16.8 15.2 5.6 14.9 c/w afs1500-fg676 tbd tbd tbd tbd tbd c/w
dc and power characteristics 3-8 revision 4 theta-ja junction-to-ambient thermal resistance ( ? ja ) is determined under standa rd conditions specified by jedec (jesd-51), but it has little relevance in actual performance of the product. it should be used with caution but is useful for comparing the th ermal performance of one package to another. a sample calculation showing the maximum power dissipation allowed for the afs600-fg484 package under forced convection of 1.0 m/s and 75 c ambient temperature is as follows: eq 4 where eq 5 the power consumption of a device can be calcul ated using the microsemi power calculator. the device's power consumption must be lower than the calculated maximum power dissipation by the package. if the power consumption is higher than t he device's maximum allowable power dissipation, a heat sink can be attached on to p of the case, or the airflow in side the system must be increased. theta-jb junction-to-board thermal resistance ( ? jb ) measures the ability of the pa ckage to dissipate heat from the surface of the chip to the pcb. as defined by t he jedec (jesd-51) standard, the thermal resistance from junction to board uses an isothermal ring cold plate zone concept. the ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. the cold plate is mounted on a jedec standard board with a minimum distanc e of 5.0 mm away from the package edge. theta-jc junction-to-case thermal resistance ( ? jc ) measures the ability of a devic e to dissipate heat from the surface of the chip to the top or bottom surface of the pa ckage. it is applicable for packages used with external heat sinks. constant temperature is applie d to the surface in consideration and acts as a boundary condition. this only applies to situations wher e all or nearly all of the heat is dissipated through the surface in consideration. calculation for heat sink for example, in a design implemented in an afs600- fg484 package with 2.5 m/s airflow, the power consumption value using the power calcul ator is 3.00 w. the user-dependent t a and t j are given as follows: from the datasheet: eq 6 ? ja = 19.00c/w (taken from table 3-6 on page 3-7 ). t a = 75.00c t j = 100.00c t a = 70.00c ? ja = 17.00c/w ? jc = 8.28c/w maximum power allowed t j(max) t a(max) ? ? ja --------------------------------------------- = maximum power allowed 100.00c 75.00c ? 19.00c/w ---------------------------------------------------- 1.3 w == p t j t a ? ? ja ------------------ - 100c 70c ? 17.00 w ----------------------------------- - 1.76 w == =
fusion family of mixed signal fpgas revision 4 3-9 the 1.76 w power is less than the required 3.00 w. the design therefore requires a heat sink, or the airflow where the device is mounted should be incr eased. the design's total junction-to-air thermal resistance requirement can be estimated by eq 7 : eq 7 determining the heat sink's thermal performance proceeds as follows: eq 8 where eq 9 a heat sink with a thermal resist ance of 5.01c/w or better should be used. thermal resistance of heat sinks is a function of airflow. the heat sink perfo rmance can be significantly improved with increased airflow. carefully estimating thermal resistance is importan t in the long-term reliability of an microsemi fpga. design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device. note: the junction-to-air and junction-to-board thermal resistances are based on jedec standard (jesd-51) and assumptions made in building the model. it may not be realized in actual application and therefore should be used with a degr ee of caution. junction-to-case th ermal resistance assumes that all power is dissipated through the case. temperature and voltage derating factors ? ja = 0.37c/w = thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer ? sa = thermal resistance of the heat sink in c/w table 3-7 ? temperature and voltage derati ng factors for timing delays (normalized to t j = 70c, worst-case vcc = 1.425 v) array voltage vcc (v) junction temperature (c) ?40c 0c 25c 70c 85c 100c 1.425 0.88 0.93 0. 95 1.00 1.02 1.05 1.500 0.83 0.88 0. 90 0.95 0.96 0.99 1.575 0.80 0.85 0. 87 0.91 0.93 0.96 ? ja(total) t j t a ? p ------------------ - 100c 70c ? 3.00 w ----------------------------------- - 10.00c/w == = ? ja(total) ? jc ? cs ? sa ++ = ? sa ? ja(total) ? jc ? ? cs ? = ? sa 13.33c/w 8.28c/w ? 0.37c/w ? 5.01c/w ==
dc and power characteristics 3-10 revision 4 calculating power dissipation quiescent supply current table 3-8 ? afs1500 quiescent supply current characteristics parameter description conditions temp. min. typ. max. unit icc 1 1.5 v quiescent current operational standby 4 , vcc = 1.575 v t j =25c 20 40 ma t j =85c 32 65 ma t j = 100c 59 120 ma standby mode 5 or sleep mode 6 , vcc = 0 v 00a icc33 2 3.3 v analog supplies current operational standby 4 , vcc33 = 3.63 v t j =25c 9.8 13 ma t j = 85c 10.7 14 ma t j = 100c 10.8 15 ma operational standby, only analog quad and ?3.3 v output on, vcc33 = 3.63 v t j =25c 0.31 2 ma t j =85c 0.35 2 ma t j = 100c 0.45 2 ma standby mode 5 , vcc33 = 3.63 v t j = 25c 2.9 3.6 ma t j =85c 2.9 4 ma t j = 100c 3.3 6 ma sleep mode 6 , vcc33 = 3.63 v t j =25c 17 19 a t j =85c 18 20 a t j = 100c 24 25 a icci 3 i/o quiescent current operational standby 4 , standby mode, and sleep mode 6 , vccix = 3.63 v t j = 25c 417 649 a t j = 85c 417 649 a t j = 100c 417 649 a notes: 1. icc is the 1.5 v power supplies, icc and icc15a. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, icci2, and icci4. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjtag = vpump = 0 v.
fusion family of mixed signal fpgas revision 4 3-11 ijtag jtag i/o quiescent current operational standby 4 , vjtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , vjtag = 0 v 00a ipp programming supply current non-programming mode, vpump = 3.63 v t j =25c 39 80 a t j =85c 40 80 a t j = 100c 40 80 a standby mode 5 or sleep mode 6 , vpump = 0 v 00a iccnvm embedded nvm current reset asserted, v ccnvm = 1.575 v t j = 25c 50 150 a t j =85c 50 150 a t j = 100c 50 150 a iccpll 1.5 v pll quiescent current operational standby , vccpll = 1.575 v t j = 25c 130 200 a t j = 85c 130 200 a t j = 100c 130 200 a table 3-8 ? afs1500 quiescent supply current characteristics (continued) parameter description conditions temp. min. typ. max. unit notes: 1. icc is the 1.5 v power supplies, icc and icc15a. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, icci2, and icci4. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjtag = vpump = 0 v.
dc and power characteristics 3-12 revision 4 table 3-9 ? afs600 quiescent supply current characteristics parameter description condi tions temp. min typ max unit icc 1 1.5 v quiescent current operational standby 4 , vcc = 1.575 v t j =25c 13 25 ma t j =85c 20 45 ma t j =100c 25 75 ma standby mode 5 or sleep mode 6 , vcc = 0 v 00a icc33 2 3.3 v analog supplies current operational standby 4 , vcc33 = 3.63 v t j = 25c 9.8 13 ma t j = 85c 10.7 14 ma t j = 100c 10.8 15 ma operational standby, only analog quad and ?3.3 v output on, vcc33 = 3.63 v t j =25c 0.31 2 ma t j =85c 0.35 2 ma t j = 100c 0.45 2 ma standby mode 5 , vcc33 = 3.63 v t j = 25c 2.8 3.6 ma t j =85c 2.9 4 ma t j = 100c 3.5 6 ma sleep mode 6 , v cc33 = 3.63 v t j =25c 17 19 a t j =85c 18 20 a t j = 100c 24 25 a icci 3 i/o quiescent current operational standby 4 , vccix = 3.63 v t j = 25c 417 648 a t j = 85c 417 648 a t j = 100c 417 649 a ijtag jtag i/o quiescent current operational standby 4 , vjtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , vjtag = 0 v 00a notes: 1. icc is the 1.5 v power supplies, icc and icc15a. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, icci2, and icci4. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjtag = vpump = 0 v.
fusion family of mixed signal fpgas revision 4 3-13 ipp programming supply current non-programming mode, vpump = 3.63 v t j =25c 36 80 a t j =85c 36 80 a t j = 100c 36 80 a standby mode 5 or sleep mode 6 , vpump = 0 v 00a iccnvm embedded nvm current reset asserted, vccnvm = 1.575 v t j =25c 22 80 a t j =85c 24 80 a t j = 100c 25 80 a iccpll 1.5 v pll quiescent current operational standby, vccpll = 1.575 v t j = 25c 130 200 a t j = 85c 130 200 a t j = 100c 130 200 a table 3-9 ? afs600 quiescent supply current characteristics (continued) parameter description condi tions temp. min typ max unit notes: 1. icc is the 1.5 v power supplies, icc and icc15a. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, icci2, and icci4. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjtag = vpump = 0 v.
dc and power characteristics 3-14 revision 4 table 3-10 ? afs250 quiescent supply current characteristics parameter description condi tions temp. min typ max unit icc 1 1.5 v quiescent current operational standby 4 , vcc = 1.575 v t j = 25c 4.8 10 ma t j = 85c 8.2 30 ma t j = 100c 15 50 ma standby mode 5 or sleep mode 6 , vcc = 0 v 00a icc33 2 3.3 v analog supplies current operational standby 4 , vcc33 = 3.63 v t j = 25c 9.8 13 ma t j = 85c 9.8 14 ma t j = 100c 10.8 15 ma operational standby, only analog quad and ?3.3 v output on, vcc33 = 3.63 v t j =25c 0.29 2 ma t j =85c 0.31 2 ma t j = 100c 0.45 2 ma standby mode 5 , vcc33 = 3.63v t j = 25c 2.9 3.0 ma t j = 85c 2.9 3.1 ma t j = 100c 3.5 6 ma sleep mode 6 , vcc33 = 3.63 v t j =25c 19 18 a t j =85c 19 20 a t j = 100c 24 25 a icci 3 i/o quiescent current operational standby 6 , vccix = 3.63 v t j = 25c 266 437 a t j = 85c 266 437 a t j = 100c 266 437 a ijtag jtag i/o quiescent current operational standby 4 , vjtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , vjtag = 0 v 00a notes: 1. icc is the 1.5 v power supplies, icc, iccpll, icc15a, iccnvm. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, and icci2. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjta g = vpump = 0 v.
fusion family of mixed signal fpgas revision 4 3-15 ipp programming supply current non-programming mode, vpump = 3.63 v t j =25c 37 80 a t j =85c 37 80 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , vpump = 0 v 00a iccnvm embedded nvm current reset asserted, vccnvm = 1.575 v t j =25c 10 40 a t j =85c 14 40 a t j = 100c 14 40 a iccpll 1.5 v pll quiescent current operational standby, vccpll = 1.575 v t j = 25c 65 100 a t j = 85c 65 100 a t j = 100c 65 100 a table 3-10 ? afs250 quiescent supply current characteristics (continued) parameter description condi tions temp. min typ max unit notes: 1. icc is the 1.5 v power supplies, icc, iccpll, icc15a, iccnvm. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, and icci2. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjta g = vpump = 0 v.
dc and power characteristics 3-16 revision 4 table 3-11 ? afs090 quiescent supply current characteristics parameter description condi tions temp. min typ max unit icc 1 1.5 v quiescent current operational standby 4 , vcc = 1.575 v t j = 25c 5 7.5 ma t j = 85c 6.5 20 ma t j = 100c 14 48 ma standby mode 5 or sleep mode 6 , v cc = 0 v 00a icc33 2 3.3 v analog supplies current operational standby 4 , vcc33 = 3.63 v t j = 25c 9.8 12 ma t j = 85c 9.8 12 ma t j = 100c 10.7 15 ma operational standby, only analog quad and ?3.3 v output on, vcc33 = 3.63 v t j =25c 0.30 2 ma t j =85c 0.30 2 ma t j = 100c 0.45 2 ma standby mode 5 , vcc33 = 3.63 v t j = 25c 2.9 2.9 ma t j = 85c 2.9 3.0 ma t j = 100c 3.5 6 ma sleep mode 6 , vcc33 = 3.63 v t j = 25c 17 18 a t j =85c 18 20 a t j = 100c 24 25 a icci 3 i/o quiescent current operational standby 6 , vccix = 3.63 v t j = 25c 260 437 a t j = 85c 260 437 a t j = 100c 260 437 a ijtag jtag i/o quiescent current operational standby 4 , vjtag = 3.63 v t j = 25c 80 100 a t j = 85c 80 100 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , vjtag = 0 v 00a ipp programming supply current non-programming mode, vpump = 3.63 v t j =25c 37 80 a t j =85c 37 80 a t j = 100c 80 100 a standby mode 5 or sleep mode 6 , vpump = 0 v 00a notes: 1. icc is the 1.5 v power supplies, icc, iccpll, icc15a, iccnvm. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, and icci2. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjtag = vpump = 0 v.
fusion family of mixed signal fpgas revision 4 3-17 iccnvm embedded nvm current reset asserted, vccnvm = 1.575 v t j =25c 10 40 a t j =85c 14 40 a t j = 100c 14 40 a iccpll 1.5 v pll quiescent current operational standby, vccpll = 1.575 v t j = 25c 65 100 a t j = 85c 65 100 a t j = 100c 65 100 a table 3-11 ? afs090 quiescent supply current characteristics (continued) parameter description condi tions temp. min typ max unit notes: 1. icc is the 1.5 v power supplies, icc, iccpll, icc15a, iccnvm. 2. icc33a includes icc33a, icc33pmp, and iccosc. 3. icci includes all icci0, icci1, and icci2. 4. operational standby is when the fusion device is powered up, all blocks are used, no i/o is toggling, voltage regulator is loaded with 200 ma, vcc33pmp is on, xtal is on, and adc is on. 5. xtal is configured as high gain, vcc = vjtag = vpump = 0 v. 6. sleep mode, vcc = vjtag = vpump = 0 v.
dc and power characteristics 3-18 revision 4 power per i/o pin table 3-12 ? summary of i/o input buffer power (per pin)?default i/o software settings vcci (v) static power pdc7 (mw) 1 dynamic power pac9 (w/mhz) 2 applicable to pro i/o banks single-ended 3.3 v lvttl/lvcmos 3.3 ? 17.39 3.3 v lvttl/lvcmos ? schmitt trigger 3.3 ? 25.51 2.5 v lvcmos 2.5 ? 5.76 2.5 v lvcmos ? schmitt trigger 2.5 ? 7.16 1.8 v lvcmos 1.8 ? 2.72 1.8 v lvcmos ? schmitt trigger 1.8 ? 2.80 1.5 v lvcmos (jesd8-11) 1.5 ? 2.08 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 ? 2.00 3.3 v pci 3.3 ? 18.82 3.3 v pci ? schmitt trigger 3.3 ? 20.12 3.3 v pci-x 3.3 ? 18.82 3.3 v pci-x ? schmitt trigger 3.3 ? 20.12 voltage-referenced 3.3 v gtl 3.3 2.90 8.23 2.5 v gtl 2.5 2.13 4.78 3.3 v gtl+ 3.3 2.81 4.14 2.5 v gtl+ 2.5 2.57 3.71 hstl (i) 1.5 0.17 2.03 hstl (ii) 1.5 0.17 2.03 sstl2 (i) 2.5 1.38 4.48 sstl2 (ii) 2.5 1.38 4.48 sstl3 (i) 3.3 3.21 9.26 sstl3 (ii) 3.3 3.21 9.26 differential lvds 2.5 2.26 1.50 lvpecl 3.3 5.71 2.17 notes: 1. pdc7 is the static power (where applicable) measured on vcci. 2. pac9 is the total dynamic power measured on vcc and vcci.
fusion family of mixed signal fpgas revision 4 3-19 applicable to advanced i/o banks single-ended 3.3 v lvttl/lvcmos 3.3 ? 16.69 2.5 v lvcmos 2.5 ? 5.12 1.8 v lvcmos 1.8 ? 2.13 1.5 v lvcmos (jesd8-11) 1.5 ? 1.45 3.3 v pci 3.3 ? 18.11 3.3 v pci-x 3.3 ? 18.11 differential lvds 2.5 2.26 1.20 lvpecl 3.3 5.72 1.87 applicable to standard i/o banks 3.3 v lvttl/lvcmos 3.3 ? 16.79 2.5 v lvcmos 2.5 ? 5.19 1.8 v lvcmos 1.8 ? 2.18 1.5 v lvcmos (jesd8-11) 1.5 ? 1.52 table 3-12 ? summary of i/o input buffer power (per pin)?d efault i/o software settings (continued) vcci (v) static power pdc7 (mw) 1 dynamic power pac9 (w/mhz) 2 notes: 1. pdc7 is the static power (where applicable) measured on vcci. 2. pac9 is the total dynamic power measured on vcc and vcci.
dc and power characteristics 3-20 revision 4 table 3-13 ? summary of i/o output bu ffer power (per pin)?default i/o software settings 1 c load (pf) vcci (v) static power pdc8 (mw) 2 dynamic power pac10 (w/mhz) 3 applicable to pro i/o banks single-ended 3.3 v lvttl/lvcmos 35 3.3 ? 474.70 2.5 v lvcmos 35 2.5 ? 270.73 1.8 v lvcmos 35 1.8 ? 151.78 1.5 v lvcmos (jesd8-11) 35 1.5 ? 104.55 3.3 v pci 10 3.3 ? 204.61 3.3 v pci-x 10 3.3 ? 204.61 voltage-referenced 3.3 v gtl 10 3.3 ? 24.08 2.5 v gtl 10 2.5 ? 13.52 3.3 v gtl+ 10 3.3 ? 24.10 2.5 v gtl+ 10 2.5 ? 13.54 hstl (i) 20 1.5 7.08 26.22 hstl (ii) 20 1.5 13.88 27.22 sstl2 (i) 30 2.5 16.69 105.56 sstl2 (ii) 30 2.5 25.91 116.60 sstl3 (i) 30 3.3 26.02 114.87 sstl3 (ii) 30 3.3 42.21 131.76 differential lvds ? 2.5 7.70 89.62 lvpecl ? 3.3 19.42 168.02 applicable to advanced i/o banks single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 468.67 2.5 v lvcmos 35 2.5 ? 267.48 1.8 v lvcmos 35 1.8 ? 149.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 103.12 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 notes: 1. dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. pdc8 is the static power (where applicable) measured on vcci. 3. pac10 is the total dynamic power measured on vcc and vcci.
fusion family of mixed signal fpgas revision 4 3-21 differential lvds ? 2.5 7.74 88.92 lvpecl ? 3.3 19.54 166.52 applicable to standard i/o banks single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 431.08 2.5 v lvcmos 35 2.5 ? 247.36 1.8 v lvcmos 35 1.8 ? 128.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 89.46 table 3-13 ? summary of i/o output bu ffer power (per pin)?default i/o software settings 1 (continued) c load (pf) vcci (v) static power pdc8 (mw) 2 dynamic power pac10 (w/mhz) 3 notes: 1. dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. pdc8 is the static power (where applicable) measured on vcci. 3. pac10 is the total dynamic power measured on vcc and vcci.
dc and power characteristics 3-22 revision 4 dynamic power consumption of various internal resources table 3-14 ? different components contributing to the dynamic power consumption in fusion devices parameter definition power supply device-specific dynamic contributions units name setting afs1500 afs600 afs250 afs090 pac1 clock contribution of a global rib vcc 1.5 v 14.5 12.8 11 11 w/mhz pac2 clock contribution of a global spine vcc 1.5 v 2.5 1.9 1.6 0.8 w/mhz pac3 clock contribution of a versatile row vcc 1.5 v 0.81 w/mhz pac4 clock contribution of a versatile used as a sequential module vcc 1.5 v 0.11 w/mhz pac5 first contribution of a versatile used as a sequential module vcc 1.5 v 0.07 w/mhz pac6 second contribution of a versatile used as a sequential module vcc 1.5 v 0.29 w/mhz pac7 contribution of a versatile used as a combinatorial module vcc 1.5 v 0.29 w/mhz pac8 average contribution of a routing net vcc 1.5 v 0.70 w/mhz pac9 contribution of an i/o input pin (standard dependent) vcci see table 3-12 on page 3-18 pac10 contribution of an i/o output pin (standard dependent) vcci see table 3-13 on page 3-20 pac11 average contribution of a ram block during a read operation vcc 1.5 v 25 w/mhz pac12 average contribution of a ram block during a write operation vcc 1.5 v 30 w/mhz pac13 dynamic contribution for pll vcc 1.5 v 2.6 w/mhz pac15 contribution of nvm block during a read operation (f < 33mhz) vcc 1.5 v 358 w/mhz pac16 1st contribution of nvm block during a read operation (f > 33 mhz) vcc 1.5 v 12.88 mw pac17 2nd contribution of nvm block during a read operation (f > 33 mhz) vcc 1.5 v 4.8 w/mhz pac18 crystal oscillator contribution vcc33a 3.3 v 0.63 mw pac19 rc oscillator contribution vcc33a 3.3 v 3.3 mw pac20 analog block dynamic power contribution of adc vcc 1.5 v 3 mw
fusion family of mixed signal fpgas revision 4 3-23 static power consumption of various internal resources power calculation methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in the libero soc software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number a nd the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? the number of nvm blocks used in the design ? the number of analog quads used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 3-16 on page 3-27 . ? enable rates of output buffers?guidelines are provided for typical applications in table 3-17 on page 3-27 . ? read rate and write rate to the ram?guideli nes are provided for typical applications in table 3-17 on page 3-27 . ? read rate to the nvm blocks the calculation should be repeated for each clock domain defined in the design. table 3-15 ? different components contributing to the static power consumption in fusion devices parameter definition power supply device-specific static contributions units afs1500 afs600 afs250 afs090 pdc1 core static power contribution in operating mode vcc 1.5 v 18 7.5 4.50 3.00 mw pdc2 device static power contribution in standby mode vcc33a 3.3 v 0.66 mw pdc3 device static power contribution in sleep mode vcc33a 3.3 v 0.03 mw pdc4 nvm static power contribution vcc 1.5 v 1.19 mw pdc5 analog block static power contribution of adc vcc33a 3.3 v 8.25 mw pdc6 analog block static power contribution per quad vcc33a 3.3 v 3.3 mw pdc7 static contribution per input pin ? standard dependent contribution vcci see table 3-12 on page 3-18 pdc8 static contribution per input pin ? standard dependent contribution vcci see table 3-13 on page 3-20 pdc9 static contribution for pll vcc 1.5 v 2.55 mw
dc and power characteristics 3-24 revision 4 methodology total power consumption?p total operating mode, standby mode, and sleep mode p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat operating mode p stat = pdc1 + (n nvm-blocks * pdc4) + pdc5+ (n quads * pdc6) + (n inputs * pdc7) + (n outputs * pdc8) + (n plls * pdc9) n nvm-blocks is the number of nvm blocks available in the device. n quads is the number of analog quads used in the design. n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. n plls is the number of plls available in the device. standby mode p stat = pdc2 sleep mode p stat = pdc3 total dynamic power consumption?p dyn operating mode p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll + p nvm + p xtl-osc + p rc-osc + p ab standby mode p dyn = p xtl-osc sleep mode p dyn = 0 w global clock dynamic contribution?p clock operating mode p clock = (pac1 + n spine * pac2 + n row * pac3 + n s-cell * pac4) * f clk n spine is the number of global spines used in the user design?guidelines are provided in the " spine architecture" section of th e global resources chapter in the fusion and extended temperature fusion fpga fabric user's guide . n row is the number of versatile rows used in the design?guidelines are provided in the " spine architecture" section of the gl obal resources chapter in the fusion and extended temperature fusion fpga fabric user's guide . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. standby mode and sleep mode p clock = 0 w sequential cells dynamic contribution?p s-cell operating mode
fusion family of mixed signal fpgas revision 4 3-25 p s-cell = n s-cell * (pac5 + ( ? 1 / 2) * pac6) * f clk n s-cell is the number of versatiles used as sequent ial modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. ? 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 3-16 on page 3-27 . f clk is the global clock signal frequency. standby mode and sleep mode p s-cell = 0 w combinatorial cells dynamic contribution?p c-cell operating mode p c-cell = n c-cell * ( ? 1 / 2) * pac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 3-16 on page 3-27 . f clk is the global clock signal frequency. standby mode and sleep mode p c-cell = 0 w routing net dynamic contribution?p net operating mode p net = (n s-cell + n c-cell ) * ( ? 1 / 2) * pac8 * f clk n s-cell is the number versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 3-16 on page 3-27 . f clk is the global clock signal frequency. standby mode and sleep mode p net = 0 w i/o input buffer dynamic contribution?p inputs operating mode p inputs = n inputs * ( ? 2 / 2) * pac9 * f clk n inputs is the number of i/o input buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 3-16 on page 3-27 . f clk is the global clock signal frequency. standby mode and sleep mode p inputs = 0 w i/o output buffer dynamic contribution?p outputs operating mode p outputs = n outputs * ( ? 2 / 2) * ? 1 * pac10 * f clk n outputs is the number of i/o output buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 3-16 on page 3-27 . ? 1 is the i/o buffer enable rate?guidelines are provided in table 3-17 on page 3-27 . f clk is the global clock signal frequency. standby mode and sleep mode p outputs = 0 w
dc and power characteristics 3-26 revision 4 ram dynamic contribution?p memory operating mode p memory = (n blocks * pac11 * ? 2 * f read-clock ) + (n blocks * pac12 * ? 3 * f write-clock ) n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. ? 2 is the ram enable rate for read op erations?guidelines are provided in table 3-17 on page 3-27 . ? 3 the ram enable rate for write operations?guidelines are provided in table 3-17 on page 3-27 . f write-clock is the memory write clock frequency. standby mode and sleep mode p memory = 0 w pll/ccc dynamic contribution?p pll operating mode p pll = pac13 * f clkout f clkin is the input clock frequency. f clkout is the output clock frequency. 1 standby mode and sleep mode p pll = 0 w nonvolatile memory dynamic contribution?p nvm operating mode the nvm dynamic power consumption is a piecewise linear function of frequency. p nvm = n nvm-blocks * ? 4 * pac15 * f read-nvm when f read-nvm ?? 33 mhz, p nvm = n nvm-blocks * ? 4 *(pac16 + pac17 * f read-nvm when f read-nvm > 33 mhz n nvm-blocks is the number of nvm blocks used in the design (2 inafs600). ? 4 is the nvm enable rate for read operations. de fault is 0 (nvm mainly in idle state). f read-nvm is the nvm read clock frequency. standby mode and sleep mode p nvm = 0 w crystal oscillator dynamic contribution?p xtl-osc operating mode p xtl-osc = pac18 standby mode p xtl-osc = pac18 sleep mode p xtl-osc = 0 w 1. the pll dynamic contribution depends on th e input clock frequency, the number of output clock signals generated by the pll, and the frequency of each output clock. if a pll is used to generate more than one output clock, include each output clock in the formula output clock by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution.
fusion family of mixed signal fpgas revision 4 3-27 rc oscillator dynamic contribution?p rc-osc operating mode p rc-osc = pac19 standby mode and sleep mode p rc-osc = 0 w analog system dynamic contribution?p ab operating mode p ab = pac20 standby mode and sleep mode p ab = 0 w guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this m eans that the net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% , as all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8. enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when non-tristate output buffers are us ed, the enable rate should be 100%. table 3-16 ? toggle rate guidelines reco mmended for power calculation component defini tion guideline ? 1 toggle rate of versatile outputs 10% ? 2 i/o buffer toggle rate 10% table 3-17 ? enable rate guidelines recomme nded for power calculation component definition guideline ? 1 i/o output buffer enable rate 100% ? 2 ram enable rate for read operations 12.5% ? 3 ram enable rate for write operations 12.5% ? 4 nvm enable rate for read operations 0%
dc and power characteristics 3-28 revision 4 example of power calculation this example considers a shift register with 5,000 storage tiles, including a counter and memory that stores analog information. the shift register is cl ocked at 50 mhz and stores and reads information from a ram. the device used is a commercial afs600 device operating in typical conditions. the calculation below uses the power calculation methodology previously presented and shows how to determine the dynamic and static power consum ption of resources used in the application. also included in the example is the calculation of power consumption in operating, standby, and sleep modes to illustrate the benefit of power-saving modes. global clock contribution?p clock f clk = 50 mhz number of sequential versatiles: n s-cell = 5,000 estimated number of spines: n spines = 5 estimated number of rows: n row = 313 operating mode p clock = (pac1 + n spine * pac2 + n row * pac3 + n s-cell * pac4) * f clk p clock = (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50 p clock = 41.28 mw standby mode and sleep mode p clock = 0 w logic?sequential cells, comb inational cells, and routing net contributions?p s-cell , p c-cell , and p net f clk = 50 mhz number of sequential versatiles: n s-cell = 5,000 number of combinatorial versatiles: n c-cell = 6,000 estimated toggle rate of versatile outputs: ? 1 = 0.1 (10%) operating mode p s-cell = n s-cell * (p ac5 + ( ? 1 / 2) * pac6) * f clk p s-cell = 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50 p s-cell = 21.13 mw p c-cell = n c-cell * ( ? 1 / 2) * pac7 * f clk p c-cell = 6,000 * (0.1 / 2) * 0.00029 * 50 p c-cell = 4.35 mw p net = (n s-cell + n c-cell ) * ( ? 1 / 2) * pac8 * f clk p net = (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50 p net = 19.25 mw p logic = p s-cell + p c-cell + p net p logic = 21.13 mw + 4.35 mw + 19.25 mw p logic = 44.73 mw standby mode and sleep mode
fusion family of mixed signal fpgas revision 4 3-29 p s-cell = 0 w p c-cell = 0 w p net = 0 w p logic = 0 w i/o input and output buffer contribution?p i/o this example uses lvttl 3.3 v i/o cells. the output buffers are 12 ma?capable, configured with high output slew and driving a 35 pf output load. f clk = 50 mhz number of input pins used: n inputs = 30 number of output pins used: n outputs = 40 estimated i/o buffer toggle rate: ? 2 = 0.1 (10%) estimated io buffer enable rate: ? 1 = 1 (100%) operating mode p inputs = n inputs * ( ? 2 / 2) * pac9 * f clk p inputs = 30 * (0.1 / 2) * 0.01739 * 50 p inputs = 1.30 mw p outputs = n outputs * ( ? 2 / 2) * ? 1 * pac10 * f clk p outputs = 40 * (0.1 / 2) * 1 * 0.4747 * 50 p outputs = 47.47 mw p i/o = p inputs + p outputs p i/o = 1.30 mw + 47.47 mw p i/o = 48.77 mw standby mode and sleep mode p inputs = 0 w p outputs = 0 w p i/o = 0 w ram contribution?p memory frequency of read clock: f read-clock = 10 mhz frequency of write clock: f write-clock = 10 mhz number of ram blocks: n blocks = 20 estimated ram read enable rate: ? 2 = 0.125 (12.5%) estimated ram write enable rate: ? 3 = 0.125 (12.5%) operating mode p memory = (n blocks * pac11 * ? 2 * f read-clock ) + (n blocks * pac12 * ? 3 * f write-clock ) p memory = (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10) p memory = 1.38 mw standby mode and sleep mode p memory = 0 w
dc and power characteristics 3-30 revision 4 pll/ccc contribution?p pll pll is not used in this application. p pll = 0 w nonvolatile memory?p nvm nonvolatile memory is not used in this application. p nvm = 0 w crystal oscillator?p xtl-osc the application utilizes standby mode. the cryst al oscillator is assumed to be active. operating mode p xtl-osc = pac18 p xtl-osc = 0.63 mw standby mode p xtl-osc = pac18 p xtl-osc = 0.63 mw sleep mode p xtl-osc = 0 w rc oscillator?p rc-osc operating mode p rc-osc = pac19 p rc-osc = 3.30 mw standby mode and sleep mode p rc-osc = 0 w analog system?p ab number of quads used: n quads = 4 operating mode p ab = pac20 p ab = 3.00 mw standby mode and sleep mode p ab = 0 w total dynamic power consumption?p dyn operating mode p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll + p nvm + p xtl-osc + p rc-osc + p ab p dyn = 41.28 mw + 21.1 mw + 4.35 mw + 19.25 mw + 1.30 mw + 47.47 mw + 1.38 mw + 0 + 0 + 0.63 mw + 3.30 mw + 3.00 mw p dyn = 143.06 mw standby mode p dyn = p xtl-osc p dyn = 0.63 mw sleep mode p dyn = 0 w
fusion family of mixed signal fpgas revision 4 3-31 total static power consumption?p stat number of quads used: n quads = 4 number of nvm blocks available (afs600): n nvm-blocks = 2 number of input pins used: n inputs = 30 number of output pins used: n outputs = 40 operating mode p stat = pdc1 + (n nvm-blocks * pdc4) + pdc5 + (n quads * pdc6) + (n inputs * pdc7) + (n outputs * pdc8) p stat = 7.50 mw + (2 * 1.19 mw) + 8.25 mw + (4 * 3.30 mw) + (30 * 0.00) + (40 * 0.00) p stat = 31.33 mw standby mode p stat = pdc2 p stat = 0.03 mw sleep mode p stat = pdc3 p stat = 0.03 mw total power consumption?p total in operating mode, the total power co nsumption of the device is 174.39 mw: p total = p stat + p dyn p total = 143.06 mw + 31.33 mw p total = 174.39 mw in standby mode, the total power consumptio n of the device is limited to 0.66 mw: p total = p stat + p dyn p total = 0.03 mw + 0.63 mw p total = 0.66 mw in sleep mode, the total power consumption of the device drops as low as 0.03 mw: p total = p stat + p dyn p total = 0.03 mw
dc and power characteristics 3-32 revision 4 power consumption table 3-18 ? power consumption parameter description condition min. typical max. units crystal oscillator istbxtal standby current of crystal oscillator 10 a idynxtal operating current rc 0.6 ma 0.032?0.2 0.19 ma 0.2?2.0 0.6 ma 2.0?20.0 0.6 ma rc oscillator idynrc operating current 1 ma acm operating current (fixed clock) 200 a/mhz operating current (user clock) 30 a nvm system nvm array operating power idle 795 a read operation see table 3-15 on page 3-23 . see table 3-15 on page 3-23 . erase 900 a write 900 a pnvmctrl nvm controller operating power 20 w/mhz
revision 4 4-1 4 ? package pin assignments qn108 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/default.aspx . note: the die attach paddle center of th e package is tied to ground (gnd). a1 b41 b52 a44 a56 b26 b14 a28 a15 a14 b1 b13 a43 a29 b40 b27 pin a1 mark
package pin assignments 4-2 revision 4 qn108 pin number afs090 function a1 nc a2 gndq a3 gaa2/io52pdb3v0 a4 gnd a5 gfa1/io47pdb3v0 a6 geb1/io45pdb3v0 a7 vccosc a8 xtal2 a9 gea1/io44ppb3v0 a10 gea0/io44npb3v0 a11 geb2/io42pdb3v0 a12 vccnvm a13 vcc15a a14 pcap a15 nc a16 gnda a17 av0 a18 ag0 a19 atrtn0 a20 at1 a21 ac1 a22 av2 a23 ag2 a24 at2 a25 at3 a26 ac3 a27 gndaq a28 adcgndref a29 nc a30 gnda a31 ptem a32 gndnvm a33 vpump a34 tck a35 tms a36 trst a37 gdb1/io39psb1v0 a38 gdc1/io38pdb1v0 a39 gnd a40 gcb1/io35pdb1v0 a41 gcb2/io33pdb1v0 a42 gba2/io31pdb1v0 a43 nc a44 gba1/io30rsb0v0 a45 gbb1/io28rsb0v0 a46 gnd a47 vcc a48 gbc1/io26rsb0v0 a49 io21rsb0v0 a50 io19rsb0v0 a51 io09rsb0v0 a52 gac0/io04rsb0v0 a53 vccib0 a54 gnd a55 gab0/io02rsb0v0 a56 gaa0/io00rsb0v0 b1 vcompla b2 vccib3 b3 gab2/io52ndb3v0 b4 vccib3 b5 gfa0/io47ndb3v0 b6 geb0/io45ndb3v0 b7 xtal1 b8 gndosc b9 gec2/io43psb3v0 b10 gea2/io42ndb3v0 b11 vcc b12 gndnvm b13 ncap b14 vcc33pmp b15 vcc33n b16 gndaq b17 ac0 b18 at0 b19 ag1 b20 av1 qn108 pin number afs090 function b21 ac2 b22 atrtn1 b23 ag3 b24 av3 b25 vcc33a b26 varef b27 pub b28 vcc33a b29 ptbase b30 vccnvm b31 vcc b32 tdi b33 tdo b34 vjtag b35 gdc0/io38ndb1v 0 b36 vccib1 b37 gcb0/io35ndb1v0 b38 gcc2/io33ndb1v 0 b39 gbb2/io31ndb1v0 b40 vccib1 b41 gndq b42 gba0/io29rsb0v0 b43 vccib0 b44 gbb0/io27rsb0v0 b45 gbc0/io25rsb0v0 b46 io20rsb0v0 b47 io10rsb0v0 b48 gac1/io05rsb0v0 b49 gab1/io03rsb0v0 b50 vcc b51 gaa1/io01rsb0v0 b52 vccpla qn108 pin number afs090 function
fusion family of mixed signal fpgas revision 4 4-3 qn180 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/default.aspx . note: the die attach paddle center of th e package is tied to ground (gnd). a1 b1 c1 a16 b15 c14 a48 pin a1 mark optional corner pad (4x) a49 a64 a32 a17 b45 b46 b60 b30 b16 c42 c43 c56 c28 c15 a33 b31 c29 d4 d3 d1 d2
package pin assignments 4-4 revision 4 qn180 pin number afs090 function afs250 function a1 gndq gndq a2 vccib3 vccib3 a3 gab2/io52ndb3v0 io74ndb3v0 a4 gfa2/io51ndb3v0 io71ndb3v0 a5 gfc2/io50ndb3v0 io69npb3v0 a6 vccib3 vccib3 a7 gfa1/io47ppb3v0 gfb1/io67ppb3v0 a8 geb0/io45ndb3v0 nc a9 xtal1 xtal1 a10 gndosc gndosc a11 gec2/io43ppb3v0 gea1/io61ppb3v0 a12 io43npb3v0 g ea0/io61npb3v0 a13 nc vccib3 a14 gndnvm gndnvm a15 pcap pcap a16 vcc33pmp vcc33pmp a17 nc nc a18 av0 av0 a19 ag0 ag0 a20 atrtn0 atrtn0 a21 ag1 ag1 a22 ac1 ac1 a23 av2 av2 a24 at2 at2 a25 at3 at3 a26 ac3 ac3 a27 av4 av4 a28 ac4 ac4 a29 at4 at4 a30 nc ag5 a31 nc av5 a32 adcgndref adcgndref a33 vcc33a vcc33a a34 gnda gnda a35 ptbase ptbase a36 vccnvm vccnvm a37 vpump vpump a38 tdi tdi a39 tdo tdo a40 vjtag vjtag a41 gdb1/io39ppb1v0 gda1/io54ppb1v0 a42 gdc1/io38pdb1v0 gdb1/io53pdb1v0 a43 vcc vcc a44 gcb0/io35npb1v0 gcb0/io48npb1v0 a45 gcc1/io34pdb1v 0 gcc1/io47pdb1v0 a46 vccib1 vccib1 a47 gbc2/io32ppb1v0 gbb2/io41ppb1v0 a48 vccib1 vccib1 a49 nc nc a50 gba0/io29rsb0 v0 gbb1/io37rsb0v0 a51 vccib0 vccib0 a52 gbb0/io27rsb0 v0 gbc0/io34rsb0v0 a53 gbc1/io26rsb0v0 io33rsb0v0 a54 io24rsb0v0 io29rsb0v0 a55 io21rsb0v0 io26rsb0v0 a56 vccib0 vccib0 a57 io15rsb0v0 io21rsb0v0 a58 io10rsb0v0 io13rsb0v0 a59 io07rsb0v0 io10rsb0v0 a60 gac0/io04rsb0v0 io06rsb0v0 a61 gab1/io03rsb0 v0 gac1/io05rsb0v0 a62 vcc vcc a63 gaa1/io01rsb0 v0 gab0/io02rsb0v0 a64 nc nc b1 vcompla vcompla b2 gaa2/io52pdb3v0 gac2/io74pdb3v0 b3 gac2/io51pdb3v0 gfa2/io71pdb3v0 b4 gfb2/io50pdb3v0 gfb2/io70psb3v0 b5 vcc vcc b6 gfc0/io49ndb3v0 gfc0/io68ndb3v0 b7 geb1/io45pdb3v0 nc b8 vccosc vccosc qn180 pin number afs090 function afs250 function
fusion family of mixed signal fpgas revision 4 4-5 b9 xtal2 xtal2 b10 gea0/io44ndb3v0 gfa0/io66ndb3v0 b11 geb2/io42pdb3v0 io60ndb3v0 b12 vcc vcc b13 vccnvm vccnvm b14 vcc15a vcc15a b15 ncap ncap b16 vcc33n vcc33n b17 gndaq gndaq b18 ac0 ac0 b19 at0 at0 b20 at1 at1 b21 av1 av1 b22 ac2 ac2 b23 atrtn1 atrtn1 b24 ag3 ag3 b25 av3 av3 b26 ag4 ag4 b27 atrtn2 atrtn2 b28 nc ac5 b29 vcc33a vcc33a b30 varef varef b31 pub pub b32 ptem ptem b33 gndnvm gndnvm b34 vcc vcc b35 tck tck b36 tms tms b37 trst trst b38 gdb2/io41psb1v0 gda2/io55psb1v0 b39 gdc0/io38ndb1v0 gdb0/io53ndb1v0 b40 vccib1 vccib1 b41 gca1/io36pdb1v0 gca1/io49pdb1v0 b42 gcc0/io34ndb1v0 gcc0/io47ndb1v0 b43 gcb2/io33psb1v0 gbc2/io42psb1v0 b44 vcc vcc qn180 pin number afs090 function afs250 function b45 gba2/io31pdb1v0 gba2/io40pdb1v0 b46 gndq gndq b47 gba1/io30rsb0 v0 gba0/io38rsb0v0 b48 gbb1/io28rsb0 v0 gbc1/io35rsb0v0 b49 vcc vcc b50 gbc0/io25rsb0v0 io31rsb0v0 b51 io23rsb0v0 io28rsb0v0 b52 io20rsb0v0 io25rsb0v0 b53 vcc vcc b54 io11rsb0v0 io14rsb0v0 b55 io08rsb0v0 io11rsb0v0 b56 gac1/io05rsb0v0 io08rsb0v0 b57 vccib0 vccib0 b58 gab0/io02rsb0 v0 gac0/io04rsb0v0 b59 gaa0/io00rsb0 v0 gaa1/io01rsb0v0 b60 vccpla vccpla c1 nc nc c2 nc vccib3 c3 gnd gnd c4 nc gfc2/io69ppb3v0 c5 gfc1/io49pdb3v0 gfc1/io68pdb3v0 c6 gfa0/io47npb3v0 gfb0/io67npb3v0 c7 vccib3 nc c8 gnd gnd c9 gea1/io44pdb3v0 gfa1/io66pdb3v0 c10 gea2/io42ndb3v0 gec2/io60pdb3v0 c11 nc gea2/io58psb3v0 c12 nc nc c13 gnd gnd c14 nc nc c15 nc nc c16 gnda gnda c17 nc nc c18 nc nc c19 nc nc c20 nc nc qn180 pin number afs090 function afs250 function
package pin assignments 4-6 revision 4 c21 ag2 ag2 c22 nc nc c23 nc nc c24 nc nc c25 nc at5 c26 gndaq gndaq c27 nc nc c28 nc nc c29 nc nc c30 nc nc c31 gnd gnd c32 nc nc c33 nc nc c34 nc nc c35 gnd gnd c36 gdb0/io39npb1v0 gda0/io54npb1v0 c37 gda1/io37nsb1 v0 gdc0/io52nsb1v0 c38 gca0/io36ndb1v0 gca0/io49ndb1v0 c39 gcb1/io35ppb1v0 gcb1/io48ppb1v0 c40 gnd gnd c41 gca2/io32npb1v0 io41npb1v0 c42 gbb2/io31ndb1v0 io40ndb1v0 c43 nc nc c44 nc gba1/io39rsb0v0 c45 nc gbb0/io36rsb0v0 c46 gnd gnd c47 nc io30rsb0v0 c48 io22rsb0v0 io27rsb0v0 c49 gnd gnd c50 io13rsb0v0 io16rsb0v0 c51 io09rsb0v0 io12rsb0v0 c52 io06rsb0v0 io09rsb0v0 c53 gnd gnd c54 nc gab1/io03rsb0v0 c55 nc gaa0/io00rsb0v0 c56 nc nc qn180 pin number afs090 function afs250 function d1 nc nc d2 nc nc d3 nc nc d4 nc nc qn180 pin number afs090 function afs250 function
fusion family of mixed signal fpgas revision 4 4-7 pq208 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/default.aspx . 208-pin pqfp 1 208
package pin assignments 4-8 revision 4 pq208 pin number afs250 function afs600 function 1 vccpla vccpla 2 vcompla vcompla 3 gndq gaa2/io85pdb4v0 4 vccib3 io85ndb4v0 5 gaa2/io76pdb3v0 gab2/io84pdb4v0 6 io76ndb3v0 io84ndb4v0 7 gab2/io75pdb3v0 ga c2/io83pdb4v0 8 io75ndb3v0 io83ndb4v0 9ncio77pdb4v0 10 nc io77ndb4v0 11 vcc io76pdb4v0 12 gnd io76ndb4v0 13 vccib3 vcc 14 io72pdb3v0 gnd 15 io72ndb3v0 vccib4 16 gfa2/io71pdb3v0 gfa2/io75pdb4v0 17 io71ndb3v0 io75ndb4v0 18 gfb2/io70pdb3v0 gfc2/io73pdb4v0 19 io70ndb3v0 io73ndb4v0 20 gfc2/io69pdb3v0 vccosc 21 io69ndb3v0 xtal1 22 vcc xtal2 23 gnd gndosc 24 vccib3 gfc1/io72pdb4v0 25 gfc1/io68pdb3v0 gfc0/io72ndb4v0 26 gfc0/io68ndb3v0 gfb1/io71pdb4v0 27 gfb1/io67pdb3v0 gfb0/io71ndb4v0 28 gfb0/io67ndb3v0 gfa1/io70pdb4v0 29 vccosc gfa0/io70ndb4v0 30 xtal1 io69pdb4v0 31 xtal2 io69ndb4v0 32 gndosc vcc 33 geb1/io62pdb3v0 gnd 34 geb0/io62ndb3v0 vccib4 35 gea1/io61pdb3v0 gec1/io63pdb4v0 36 gea0/io61ndb3v0 gec0/io63ndb4v0 37 gec2/io60pdb3v0 geb1/io62pdb4v0 38 io60ndb3v0 geb0/io62ndb4v0 39 gnd gea1/io61pdb4v0 40 vccib3 gea0/io61ndb4v0 41 geb2/io59pdb3v0 gec2/io60pdb4v0 42 io59ndb3v0 io60ndb4v0 43 gea2/io58pdb3v0 vccib4 44 io58ndb3v0 gndq 45 vcc vcc 45 vcc vcc 46 vccnvm vccnvm 47 gndnvm gndnvm 48 gnd gnd 49 vcc15a vcc15a 50 pcap pcap 51 ncap ncap 52 vcc33pmp vcc33pmp 53 vcc33n vcc33n 54 gnda gnda 55 gndaq gndaq 56 nc av0 57 nc ac0 58 nc ag0 59 nc at0 60 nc atrtn0 61 nc at1 62 nc ag1 63 nc ac1 64 nc av1 65 av0 av2 66 ac0 ac2 67 ag0 ag2 68 at0 at2 69 atrtn0 atrtn1 70 at1 at3 71 ag1 ag3 72 ac1 ac3 73 av1 av3 pq208 pin number afs250 function afs600 function
fusion family of mixed signal fpgas revision 4 4-9 74 av2 av4 75 ac2 ac4 76 ag2 ag4 77 at2 at4 78 atrtn1 atrtn2 79 at3 at5 80 ag3 ag5 81 ac3 ac5 82 av3 av5 83 av4 av6 84 ac4 ac6 85 ag4 ag6 86 at4 at6 87 atrtn2 atrtn3 88 at5 at7 89 ag5 ag7 90 ac5 ac7 91 av5 av7 92 nc av8 93 nc ac8 94 nc ag8 95 nc at8 96 nc atrtn4 97 nc at9 98 nc ag9 99 nc ac9 100 nc av9 101 gndaq gndaq 102 vcc33a vcc33a 103 adcgndref adcgndref 104 varef varef 105 pub pub 106 vcc33a vcc33a 107 gnda gnda 108 ptem ptem 109 ptbase ptbase 110 gndnvm gndnvm pq208 pin number afs250 function afs600 function 111 vccnvm vccnvm 112 vcc vcc 112 vcc vcc 113 vpump vpump 114 gndq nc 115 vccib1 tck 116 tck tdi 117 tdi tms 118 tms tdo 119 tdo trst 120 trst vjtag 121 vjtag io57ndb2v0 122 io57ndb1v0 gdc2/io57pdb2v0 123 gdc2/io57pdb1v0 io56ndb2v0 124 io56ndb1v0 gdb2/io56pdb2v0 125 gdb2/io56pdb1v0 io55ndb2v0 126 vccib1 gda2/io55pdb2v0 127 gnd gda0/io54ndb2v0 128 io55ndb1v0 gda1/io54pdb2v0 129 gda2/io55pdb1v0 vccib2 130 gda0/io54ndb1v0 gnd 131 gda1/io54pdb1v0 vcc 132 gdb0/io53ndb1v0 gca0/io45ndb2v0 133 gdb1/io53pdb1 v0 gca1/io45pdb2v0 134 gdc0/io52ndb1v0 gcb0/io44ndb2v0 135 gdc1/io52pdb1v0 gcb1/io44pdb2v0 136 io51nsb1v0 gcc0/io43ndb2v 0 137 vccib1 gcc1/io43pdb2v0 138 gnd io42ndb2v0 139 vcc io42pdb2v0 140 io50ndb1v0 io41ndb2v0 141 io50pdb1v0 gcc2/io41pdb2v0 142 gca0/io49ndb1v0 vccib2 143 gca1/io49pdb1v0 gnd 144 gcb0/io48ndb1v0 vcc 145 gcb1/io48pdb1v0 io40ndb2v0 146 gcc0/io47ndb1v0 gcb2/io40pdb2v0 pq208 pin number afs250 function afs600 function
package pin assignments 4-10 revision 4 147 gcc1/io47pdb1v0 io39ndb2v0 148 io42ndb1v0 gca2/io39pdb2v0 149 gbc2/io42pdb1v0 io31ndb2v0 150 vccib1 gbb2/io31pdb2v0 151 gnd io30ndb2v0 152 vcc gba2/io30pdb2v0 153 io41ndb1v0 vccib2 154 gbb2/io41pdb1v0 gndq 155 io40ndb1v0 vcomplb 156 gba2/io40pdb1v0 vccplb 157 gba1/io39rsb0v0 vccib1 158 gba0/io38rsb0v0 gndq 159 gbb1/io37rsb0v0 gbb1/io27ppb1v1 160 gbb0/io36rsb0v0 gba1/io28ppb1v1 161 gbc1/io35rsb0v0 gbb0/io27npb1v1 162 vccib0 gba0/io28npb1v1 163 gnd vccib1 164 vcc gnd 165 gbc0/io34rsb0v0 vcc 166 io33rsb0v0 gbc1/io26pdb1v1 167 io32rsb0v0 gbc0/io26ndb1v1 168 io31rsb0v0 io24ppb1v1 169 io30rsb0v0 io23ppb1v1 170 io29rsb0v0 io24npb1v1 171 io28rsb0v0 io23npb1v1 172 io27rsb0v0 io22ppb1v0 173 io26rsb0v0 io21ppb1v0 174 io25rsb0v0 io22npb1v0 175 vccib0 io21npb1v0 176 gnd io20psb1v0 177 vcc io19psb1v0 178 io24rsb0v0 io14nsb0v1 179 io23rsb0v0 io12pdb0v1 180 io22rsb0v0 io12ndb0v1 181 io21rsb0v0 vccib0 182 io20rsb0v0 gnd 183 io19rsb0v0 vcc pq208 pin number afs250 function afs600 function 184 io18rsb0v0 io10ppb0v1 185 io17rsb0v0 io09ppb0v1 186 io16rsb0v0 io10npb0v1 187 io15rsb0v0 io09npb0v1 188 vccib0 io08ppb0v1 189 gnd io07ppb0v1 190 vcc io08npb0v1 191 io14rsb0v0 io07npb0v1 192 io13rsb0v0 io06ppb0v0 193 io12rsb0v0 io05ppb0v0 194 io11rsb0v0 io06npb0v0 195 io10rsb0v0 io04ppb0v0 196 io09rsb0v0 io05npb0v0 197 io08rsb0v0 io04npb0v0 198 io07rsb0v0 gac1/io03pdb0v0 199 io06rsb0v0 gac0/io03ndb0v0 200 gac1/io05rsb0v0 vccib0 201 vccib0 gnd 202 gnd vcc 203 vcc gab1/io02pdb0v0 204 gac0/io04rsb0v0 gab0/io02ndb0v0 205 gab1/io03rsb0v0 gaa1/io01pdb0v0 206 gab0/io02rsb0v0 gaa0/io01ndb0v0 207 gaa1/io01rsb0v0 gndq 208 gaa0/io00rsb0v0 vccib0 pq208 pin number afs250 function afs600 function
fusion family of mixed signal fpgas revision 4 4-11 fg256 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/default.aspx . 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
package pin assignments 4-12 revision 4 fg256 pin number afs090 function afs250 func tion afs600 function afs1500 function a1gndgndgndgnd a2 vccib0 vccib0 vccib0 vccib0 a3 gab0/io02rsb0v0 gaa0 /io00rsb0v0 gaa0/io01ndb0v0 gaa0/io01ndb0v0 a4 gab1/io03rsb0v0 gaa1 /io01rsb0v0 gaa1/io01pdb0v0 gaa1/io01pdb0v0 a5gndgndgndgnd a6 io07rsb0v0 io11rsb0v0 io10pdb0v1 io07pdb0v1 a7 io10rsb0v0 io14rsb0v0 io12pdb0v1 io13pdb0v2 a8 io11rsb0v0 io15rsb0v0 io12ndb0v1 io13ndb0v2 a9 io16rsb0v0 io24rsb0v0 io22ndb1v0 io24ndb1v0 a10 io17rsb0v0 io25rsb0v0 io22pdb1v0 io24pdb1v0 a11 io18rsb0v0 io26rsb0v0 io24ndb1v1 io29ndb1v1 a12 gnd gnd gnd gnd a13 gbc0/io25rsb0v0 gba0 /io38rsb0v0 gba0/io28ndb1v1 gba0/io42ndb1v2 a14 gba0/io29rsb0v0 io32rsb0 v0 io29ndb1v1 io43ndb1v2 a15 vccib0 vccib0 vccib1 vccib1 a16 gnd gnd gnd gnd b1 vcompla vcompla vcompla vcompla b2 vccpla vccpla vccpla vccpla b3 gaa0/io00rsb0v0 io07rsb0 v0 io00ndb0v0 io00ndb0v0 b4 gaa1/io01rsb0v0 io06rsb0v0 io00pdb0v0 io00pdb0v0 b5 nc gab1/io03rsb0v0 gab1/ io02ppb0v0 gab1/io02ppb0v0 b6 io06rsb0v0 io10rsb0v0 io10ndb0v1 io07ndb0v1 b7 vccib0 vccib0 vccib0 vccib0 b8 io12rsb0v0 io16rsb0v0 io18ndb1v0 io22ndb1v0 b9 io13rsb0v0 io17rsb0v0 io18pdb1v0 io22pdb1v0 b10 vccib0 vccib0 vccib1 vccib1 b11 io19rsb0v0 io27rsb0v0 io24pdb1v1 io29pdb1v1 b12 gbb0/io27rsb0v0 gbc0 /io34rsb0v0 gbc0/io26n pb1v1 gbc0/io40npb1v2 b13 gbc1/io26rsb0v0 gba1 /io39rsb0v0 gba1/io28pdb1v1 gba1/io42pdb1v2 b14 gba1/io30rsb0v0 io33rsb0v0 io29pdb1v1 io43pdb1v2 b15 nc nc vccplb vccplb b16 nc nc vcomplb vcomplb c1 vccib3 v cci b3 vccib4 vccib4 c2 gnd gnd gnd gnd c3 vccib3 vccib3 vccib4 vccib4 c4 nc nc vccib0 vccib0 c5 vccib0 vccib0 vccib0 vccib0 c6 gac1/io05rsb0v0 gac1/io05rsb0v0 gac1/io03pdb0v0 gac1/io03pdb0v0
fusion family of mixed signal fpgas revision 4 4-13 c7 io09rsb0v0 io12rsb0v0 io06ndb0v0 io09ndb0v1 c8 io14rsb0v0 io22rsb0v0 io16pdb1v0 io23pdb1v0 c9 io15rsb0v0 io23rsb0v0 io16ndb1v0 io23ndb1v0 c10 io22rsb0v0 io30rsb0v0 io25ndb1v1 io31ndb1v1 c11 io20rsb0v0 io31rsb0v0 io25pdb1v1 io31pdb1v1 c12 vccib0 vccib0 vccib1 vccib1 c13 gbb1/io28rsb0v0 gbc 1/io35rsb0v0 gb c1/io26ppb1v1 gb c1/io40ppb1v2 c14 vccib1 vccib1 vccib2 vccib2 c15 gnd gnd gnd gnd c16 vccib1 vccib1 vccib2 vccib2 d1 gfc2/io50npb3v0 io75ndb3v0 io84ndb4v0 io124ndb4v0 d2 gfa2/io51ndb3v0 gab2/io75pdb3v0 gab2/io84pdb4v0 gab2/io124pdb4v0 d3 gac2/io51pdb3v0 io76ndb3v0 io85ndb4v0 io125ndb4v0 d4 gaa2/io52pdb3v0 gaa2 /io76pdb3v0 gaa2/io85pdb4v0 gaa2/io125pdb4v0 d5 gab2/io52ndb3v0 gab0/io02rsb0v0 gab0/io02npb0v0 gab0/io02npb0v0 d6 gac0/io04rsb0v0 gac0/io04rsb0v0 gac0/io03ndb0v0 gac0/io03ndb0v0 d7 io08rsb0v0 io13rsb0v0 io06pdb0v0 io09pdb0v1 d8 nc io20rsb0v0 io14ndb0v1 io15ndb0v2 d9 nc io21rsb0v0 io14pdb0v1 io15pdb0v2 d10 io21rsb0v0 io28rsb0v0 io23pdb1v1 io37pdb1v2 d11 io23rsb0v0 gbb0/io36rsb0v0 g bb0/io27ndb1v1 gbb0/io41ndb1v2 d12 nc nc vccib1 vccib1 d13 gba2/io31pdb1v0 gba2 /io40pdb1v0 gba2/io30pdb2v0 gba2/io44pdb2v0 d14 gbb2/io31ndb1v0 io40ndb1v0 io30ndb2v0 io44ndb2v0 d15 gbc2/io32pdb1v0 gbb2 /io41pdb1v0 gbb2/io31pdb2v0 gbb2/io45pdb2v0 d16 gca2/io32ndb1v0 io41ndb1v0 io31ndb2v0 io45ndb2v0 e1gndgndgndgnd e2 gfb0/io48npb3v0 io73ndb3v0 io81ndb4v0 io118ndb4v0 e3 gfb2/io50ppb3v0 io73pdb3v0 io81pdb4v0 io118pdb4v0 e4 vccib3 vccib3 vccib4 vccib4 e5 nc io74npb3v0 io83npb4v0 io123npb4v0 e6 nc io08rsb0v0 io04npb0v0 io05npb0v1 e7gndgndgndgnd e8 nc io18rsb0v0 io08pdb0v1 io11pdb0v1 e9 nc nc io20ndb1v0 io27ndb1v1 e10 gnd gnd gnd gnd e11 io24rsb0v0 gbb1/io37rsb0v0 gb b1/io27pdb1v1 gbb1/io41pdb1v2 e12 nc io50ppb1v0 io33psb2v0 io48psb2v0 fg256 pin number afs090 function afs250 func tion afs600 function afs1500 function
package pin assignments 4-14 revision 4 e13 vccib1 vccib1 vccib2 vccib2 e14 gcc2/io33ndb1v0 io42ndb1v0 io32ndb2v0 io46ndb2v0 e15 gcb2/io33pdb1v0 gbc2 /io42pdb1v0 gbc2/io32pdb2v0 gbc2/io46pdb2v0 e16 gnd gnd gnd gnd f1 nc nc io79ndb4v0 io111ndb4v0 f2 nc nc io79pdb4v0 io111pdb4v0 f3 gfb1/io48ppb3v0 io72ndb3v 0 io76ndb4v0 io112ndb4v0 f4 gfc0/io49ndb3v0 io72pdb3v0 io76pdb4v0 io112pdb4v0 f5 nc nc io82psb4v0 io120psb4v0 f6 gfc1/io49pdb3v0 gac 2/io74ppb3v0 gac2 /io83ppb4v0 gac2/io123ppb4v0 f7 nc io09rsb0v0 io04ppb0v0 io05ppb0v1 f8 nc io19rsb0v0 io08ndb0v1 io11ndb0v1 f9 nc nc io20pdb1v0 io27pdb1v1 f10 nc io29rsb0v0 io23ndb1v1 io37ndb1v2 f11 nc io43ndb1v0 io36ndb2v0 io50ndb2v0 f12 nc io43pdb1v0 io36pdb2v0 io50pdb2v0 f13 nc io44ndb1v0 io39ndb2v0 io59ndb2v0 f14 nc gca2/io44pdb1v0 gca2/ io39pdb2v0 gca2/io59pdb2v0 f15 gcc1/io34pdb1v0 gcb2 /io45pdb1v0 gcb2/io40pdb2v0 gcb2/io60pdb2v0 f16 gcc0/io34ndb1v0 io45ndb1v0 io40ndb2v0 io60ndb2v0 g1 gec0/io46npb3v0 io70npb3 v0 io74npb4v0 io109npb4v0 g2 vccib3 vccib3 vccib4 vccib4 g3 gec1/io46ppb3v0 gfb2/io70ppb3v 0 gfb2/io74ppb4v0 gfb2/io109ppb4v0 g4 gfa1/io47pdb3v0 gfa2/io71pdb3v0 gfa2/io75pdb4v0 gfa2/io110pdb4v0 g5 gnd gnd gnd gnd g6 gfa0/io47ndb3v0 io71ndb3v0 io75ndb4v0 io110ndb4v0 g7 gnd gnd gnd gnd g8 vcc vcc vcc vcc g9 gnd gnd gnd gnd g10 vcc vcc vcc vcc g11 gda1/io37ndb1v0 gcc0/io47ndb1v0 g cc0/io43ndb2v0 gcc0/io62ndb2v0 g12 gnd gnd gnd gnd g13 io37pdb1v0 gcc1/io47pdb1v0 g cc1/io43pdb2v0 gcc1/io62pdb2v0 g14 gcb0/io35npb1v0 io46n pb1v0 io41npb2v0 io61npb2v0 g15 vccib1 vccib1 vccib2 vccib2 g16 gcb1/io35ppb1v0 gcc2/io46ppb1v0 gcc2/io41ppb2v0 gcc2/io61ppb2v0 h1 geb1/io45pdb3v0 gfc2 /io69pdb3v0 gfc2/io73pdb4v0 gfc2/io108pdb4v0 h2 geb0/io45ndb3v0 io69ndb3v0 io73ndb4v0 io108ndb4v0 fg256 pin number afs090 function afs250 func tion afs600 function afs1500 function
fusion family of mixed signal fpgas revision 4 4-15 h3 xtal2 xtal2 xtal2 xtal2 h4 xtal1 xtal1 xtal1 xtal1 h5 gndosc gndosc gndosc gndosc h6 vccosc vccosc vccosc vccosc h7 vcc vcc vcc vcc h8 gnd gnd gnd gnd h9 vcc vcc vcc vcc h10 gnd gnd gnd gnd h11 gdc0/io38ndb1v0 io51ndb1v0 io47ndb2v0 io69ndb2v0 h12 gdc1/io38pdb1v0 io51pdb1v0 io47pdb2v0 io69pdb2v0 h13 gdb1/io39pdb1v0 gca1 /io49pdb1v0 gca1/io45pdb2v0 gca1/io64pdb2v0 h14 gdb0/io39ndb1v0 gca0/io49ndb1v 0 gca0/io45ndb2v0 gca0/io64ndb2v0 h15 gca0/io36ndb1v0 gcb0/io48ndb1v 0 gcb0/io44ndb2v0 gcb0/io63ndb2v0 h16 gca1/io36pdb1v0 gcb1 /io48pdb1v0 gcb1/io44pdb2v0 gcb1/io63pdb2v0 j1 gea0/io44ndb3v0 gfa0/io66ndb3v 0 gfa0/io70ndb4v0 gfa0/io105ndb4v0 j2 gea1/io44pdb3v0 gfa1/io66pdb3v0 g fa1/io70pdb4v0 gfa1/io105pdb4v0 j3 io43ndb3v0 gfb0/io67ndb3v0 gfb 0/io71ndb4v0 gfb0/io106ndb4v0 j4 gec2/io43pdb3v0 gfb1/io67pdb3v0 g fb1/io71pdb4v0 gfb1/io106pdb4v0 j5 nc gfc0/io68ndb3v0 gfc0/io72ndb4v0 gfc0/io107ndb4v0 j6 nc gfc1/io68pdb3v0 gfc1/io72pdb4v0 gfc1/io107pdb4v0 j7gndgndgndgnd j8 vcc vcc vcc vcc j9gndgndgndgnd j10 vcc vcc vcc vcc j11 gdc2/io41npb1v0 io56npb1v0 io56npb2v0 io83npb2v0 j12 nc gdb0/io53npb1v0 gdb0/ io53npb2v0 gdb0/io80npb2v0 j13 nc gda1/io54pdb1v0 gda1/ io54pdb2v0 gda1/io81pdb2v0 j14 gda0/io40pdb1v0 gdc1/io52ppb1 v0 gdc1/io52ppb2v0 gdc1/io79ppb2v0 j15 nc io50npb1v0 io51nsb2v0 io77nsb2v0 j16 gda2/io40ndb1v0 gdc0/io52npb1v0 gdc0/io52npb2v0 gdc0/io79npb2v0 k1 nc io65npb3v0 io67npb4v0 io92npb4v0 k2 vccib3 vccib3 vccib4 vccib4 k3 nc io65ppb3v0 io67ppb4v0 io92ppb4v0 k4 nc io64pdb3v0 io65pdb4v0 io96pdb4v0 k5gndgndgndgnd k6 nc io64ndb3v0 io65ndb4v0 io96ndb4v0 k7 vcc vcc vcc vcc k8gndgndgndgnd fg256 pin number afs090 function afs250 func tion afs600 function afs1500 function
package pin assignments 4-16 revision 4 k9 vcc vcc vcc vcc k10 gnd gnd gnd gnd k11 nc gdc2/io57ppb1v0 gdc2/i o57ppb2v0 gdc2/io84ppb2v0 k12 gnd gnd gnd gnd k13 nc gda0/io54ndb1v0 gda0/io54ndb2v0 gda0/io81ndb2v0 k14 nc gda2/io55ppb1v0 gda2/i o55ppb2v0 gda2/io82ppb2v0 k15 vccib1 vccib1 vccib2 vccib2 k16 nc gdb1/io53ppb1v0 gdb1/i o53ppb2v0 gdb1/io80ppb2v0 l1 nc gec1/io63pdb3v0 gec1/io63pdb4v0 gec1/io90pdb4v0 l2 nc gec0/io63ndb3v0 gec0/io63ndb4v0 gec0/io90ndb4v0 l3 nc geb1/io62pdb3v0 geb1/i o62pdb4v0 geb1/io89pdb4v0 l4 nc geb0/io62ndb3v0 geb0/io62ndb4v0 geb0/io89ndb4v0 l5 nc io60ndb3v0 io60ndb4v0 io87ndb4v0 l6 nc gec2/io60pdb3v0 gec2/io60pdb4v0 gec2/io87pdb4v0 l7 gnda gnda gnda gnda l8ac0ac0ac2ac2 l9 av2 av2 av4 av4 l10ac3ac3ac5ac5 l11 ptem ptem ptem ptem l12 tdo tdo tdo tdo l13 vjtag vjtag vjtag vjtag l14 nc io57npb1v0 io57npb2v0 io84npb2v0 l15 gdb2/io41ppb1v0 gdb2/ io56ppb1v0 gdb2/io56 ppb2v0 gdb2/io83ppb2v0 l16 nc io55npb1v0 io55npb2v0 io82npb2v0 m1gndgndgndgnd m2 nc gea1/io61pdb3v0 gea1/i o61pdb4v0 gea1/io88pdb4v0 m3 nc gea0/io61ndb3v0 gea0/io61ndb4v0 gea0/io88ndb4v0 m4 vccib3 vccib3 vccib4 vccib4 m5 nc io58npb3v0 io58npb4v0 io85npb4v0 m6 nc nc av0 av0 m7 nc nc ac1 ac1 m8 ag1 ag1 ag3 ag3 m9ac2ac2ac4ac4 m10 ac4 ac4 ac6 ac6 m11 nc ag5 ag7 ag7 m12 vpump vpump vpump vpump m13 vccib1 vccib1 vccib2 vccib2 m14 tms tms tms tms fg256 pin number afs090 function afs250 func tion afs600 function afs1500 function
fusion family of mixed signal fpgas revision 4 4-17 m15 trst trst trst trst m16 gnd gnd gnd gnd n1 geb2/io42pdb3v0 geb2 /io59pdb3v0 geb2/io59pdb4v0 geb2/io86pdb4v0 n2 gea2/io42ndb3v0 io59ndb3v0 io59ndb4v0 io86ndb4v0 n3 nc gea2/io58ppb3v0 gea2/ io58ppb4v0 gea2/io85ppb4v0 n4 vcc33pmp vcc33pmp vcc33pmp vcc33pmp n5 vcc15a vcc15a vcc15a vcc15a n6 nc nc ag0 ag0 n7 ac1 ac1 ac3 ac3 n8 ag3 ag3 ag5 ag5 n9 av3 av3 av5 av5 n10 ag4 ag4 ag6 ag6 n11 nc nc ac8 ac8 n12 gnda gnda gnda gnda n13 vcc33a vcc33a vcc33a vcc33a n14 vccnvm vccnvm vccnvm vccnvm n15 tck tck tck tck n16 tdi tdi tdi tdi p1 vccnvm vccnvm vccnvm vccnvm p2 gndnvm gndnvm gndnvm gndnvm p3 gnda gnda gnda gnda p4 nc nc ac0 ac0 p5 nc nc ag1 ag1 p6 nc nc av1 av1 p7 ag0 ag0 ag2 ag2 p8 ag2 ag2 ag4 ag4 p9 gnda gnda gnda gnda p10 nc ac5 ac7 ac7 p11 nc nc av8 av8 p12 nc nc ag8 ag8 p13 nc nc av9 av9 p14 adcgndref adcgndref adcgndref adcgndref p15 ptbase ptbase ptbase ptbase p16 gndnvm gndnvm gndnvm gndnvm r1 vccib3 vccib3 vccib4 vccib4 r2 pcap pcap pcap pcap r3 nc nc at1 at1 r4 nc nc at0 at0 fg256 pin number afs090 function afs250 func tion afs600 function afs1500 function
package pin assignments 4-18 revision 4 r5 av0 av0 av2 av2 r6 at0 at0 at2 at2 r7 av1 av1 av3 av3 r8 at3 at3 at5 at5 r9 av4 av4 av6 av6 r10 nc at5 at7 at7 r11 nc av5 av7 av7 r12 nc nc at9 at9 r13 nc nc ag9 ag9 r14 nc nc ac9 ac9 r15 pub pub pub pub r16 vccib1 vccib1 vccib2 vccib2 t1gndgndgndgnd t2 ncap ncap ncap ncap t3 vcc33n vcc33n vcc33n vcc33n t4 nc nc atrtn0 atrtn0 t5 at1 at1 at3 at3 t6 atrtn0 atrtn0 atrtn1 atrtn1 t7 at2 at2 at4 at4 t8 atrtn1 atrtn1 atrtn2 atrtn2 t9 at4 at4 at6 at6 t10 atrtn2 atrtn2 atrtn3 atrtn3 t11 nc nc at8 at8 t12 nc nc atrtn4 atrtn4 t13 gnda gnda gnda gnda t14 vcc33a vcc33a vcc33a vcc33a t15 varef varef varef varef t16 gnd gnd gnd gnd fg256 pin number afs090 function afs250 func tion afs600 function afs1500 function
fusion family of mixed signal fpgas revision 4 4-19 fg484 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/default.aspx . a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner
package pin assignments 4-20 revision 4 fg484 pin number afs600 function afs1500 function a1 gnd gnd a2 vcc nc a3 gaa1/io01pdb0v0 gaa1/io01pdb0v0 a4 gab0/io02ndb0v0 gab0/io02ndb0v0 a5 gab1/io02pdb0v0 gab1/io02pdb0v0 a6 io07ndb0v1 io07ndb0v1 a7 io07pdb0v1 io07pdb0v1 a8 io10pdb0v1 io09pdb0v1 a9 io14ndb0v1 io13ndb0v2 a10 io14pdb0v1 io13pdb0v2 a11 io17pdb1v0 io24pdb1v0 a12 io18pdb1v0 io26pdb1v0 a13 io19ndb1v0 io27ndb1v1 a14 io19pdb1v0 io27pdb1v1 a15 io24ndb1v1 io35ndb1v2 a16 io24pdb1v1 io35pdb1v2 a17 gbc0/io26ndb1v1 gbc0/io40ndb1v2 a18 gba0/io28ndb1v1 gba0/io42ndb1v2 a19 io29ndb1v1 io43ndb1v2 a20 io29pdb1v1 io43pdb1v2 a21 vcc nc a22 gnd gnd aa1 vcc nc aa2 gnd gnd aa3 vccib4 vccib4 aa4 vccib4 vccib4 aa5 pcap pcap aa6 ag0 ag0 aa7 gnda gnda aa8 ag1 ag1 aa9 ag2 ag2 aa10 gnda gnda aa11 ag3 ag3 aa12 ag6 ag6 aa13 gnda gnda aa14 ag7 ag7 aa15 ag8 ag8 aa16 gnda gnda aa17 ag9 ag9 aa18 varef varef aa19 vccib2 vccib2 aa20 ptem ptem aa21 gnd gnd aa22 vcc nc ab1 gnd gnd ab2 vcc nc ab3 nc io94nsb4v0 ab4 gnd gnd ab5 vcc33n vcc33n ab6 at0 at0 ab7 atrtn0 atrtn0 ab8 at1 at1 ab9 at2 at2 ab10 atrtn1 atrtn1 ab11 at3 at3 ab12 at6 at6 ab13 atrtn3 atrtn3 ab14 at7 at7 ab15 at8 at8 ab16 atrtn4 atrtn4 ab17 at9 at9 ab18 vcc33a vcc33a ab19 gnd gnd ab20 nc io76npb2v0 ab21 vcc nc ab22 gnd gnd b1 vcc nc b2 gnd gnd b3 gaa0/io01ndb0v 0 gaa0/io01ndb0v0 b4 gnd gnd fg484 pin number afs600 function afs1500 function
fusion family of mixed signal fpgas revision 4 4-21 b5 io05ndb0v0 io04ndb0v0 b6 io05pdb0v0 io04pdb0v0 b7 gnd gnd b8 io10ndb0v1 io09ndb0v1 b9 io13pdb0v1 io11pdb0v1 b10 gnd gnd b11 io17ndb1v0 io24ndb1v0 b12 io18ndb1v0 io26ndb1v0 b13 gnd gnd b14 io21ndb1v0 io31ndb1v1 b15 io21pdb1v0 io31pdb1v1 b16 gnd gnd b17 gbc1/io26pdb1v1 gbc1/io40pdb1v2 b18 gba1/io28pdb1v1 gba1/io42pdb1v2 b19 gnd gnd b20 vccplb vccplb b21 gnd gnd b22 vcc nc c1 io82pdb4v0 io121pdb4v0 c2 nc io122psb4v0 c3 io00ndb0v0 io00ndb0v0 c4 io00pdb0v0 io00pdb0v0 c5 vccib0 vccib0 c6 io06ndb0v0 io05ndb0v1 c7 io06pdb0v0 io05pdb0v1 c8 vccib0 vccib0 c9 io13ndb0v1 io11ndb0v1 c10 io11pdb0v1 io14pdb0v2 c11 vccib0 vccib0 c12 vccib1 vccib1 c13 io20ndb1v0 io29ndb1v1 c14 io20pdb1v0 io29pdb1v1 c15 vccib1 vccib1 c16 io25ndb1v1 io37ndb1v2 c17 gbb0/io27ndb1v1 gbb0/io41ndb1v2 fg484 pin number afs600 function afs1500 function c18 vccib1 vccib1 c19 vcomplb vcomplb c20 gba2/io30pdb2v0 gba2/io44pdb2v0 c21 nc io48psb2v0 c22 gbb2/io31pdb2v0 gbb2/io45pdb2v0 d1 io82ndb4v0 io121ndb4v0 d2 gnd gnd d3 io83ndb4v0 io123ndb4v0 d4 gac2/io83pdb4v0 gac2/io123pdb4v0 d5 gaa2/io85pdb4v0 gaa2/io125pdb4v0 d6 gac0/io03ndb0v0 gac0/io03ndb0v0 d7 gac1/io03pdb0v0 gac1/io03pdb0v0 d8 io09ndb0v1 io10ndb0v1 d9 io09pdb0v1 io10pdb0v1 d10 io11ndb0v1 io14ndb0v2 d11 io16ndb1v0 io23ndb1v0 d12 io16pdb1v0 io23pdb1v0 d13 nc io32npb1v1 d14 io23ndb1v1 io34ndb1v1 d15 io23pdb1v1 io34pdb1v1 d16 io25pdb1v1 io37pdb1v2 d17 gbb1/io27pdb1v1 gbb1/io41pdb1v2 d18 vccib2 vccib2 d19 nc io47ppb2v0 d20 io30ndb2v0 io44ndb2v0 d21 gnd gnd d22 io31ndb2v0 io45ndb2v0 e1 io81ndb4v0 io120ndb4v0 e2 io81pdb4v0 io120pdb4v0 e3 vccib4 vccib4 e4 gab2/io84pdb4v0 gab2/io124pdb4v0 e5 io85ndb4v0 io125ndb4v0 e6 gnd gnd e7 vccib0 vccib0 e8 nc io08ndb0v1 fg484 pin number afs600 function afs1500 function
package pin assignments 4-22 revision 4 e9 nc io08pdb0v1 e10 gnd gnd e11 io15ndb1v0 io22ndb1v0 e12 io15pdb1v0 io22pdb1v0 e13 gnd gnd e14 nc io32ppb1v1 e15 nc io36npb1v2 e16 vccib1 vccib1 e17 gnd gnd e18 nc io47npb2v0 e19 io33pdb2v0 io49pdb2v0 e20 vccib2 vccib2 e21 io32ndb2v0 io46ndb2v0 e22 gbc2/io32pdb2v0 gbc2/io46pdb2v0 f1 io80ndb4v0 io118ndb4v0 f2 io80pdb4v0 io118pdb4v0 f3 nc io119nsb4v0 f4 io84ndb4v0 io124ndb4v0 f5 gnd gnd f6 vcompla vcompla f7 vccpla vccpla f8 vccib0 vccib0 f9 io08ndb0v1 io12ndb0v1 f10 io08pdb0v1 io12pdb0v1 f11 vccib0 vccib0 f12 vccib1 vccib1 f13 io22ndb1v0 io30ndb1v1 f14 io22pdb1v0 io30pdb1v1 f15 vccib1 vccib1 f16 nc io36ppb1v2 f17 nc io38npb1v2 f18 gnd gnd f19 io33ndb2v0 io49ndb2v0 f20 io34pdb2v0 io50pdb2v0 f21 io34ndb2v0 io50ndb2v0 fg484 pin number afs600 function afs1500 function f22 io35pdb2v0 io51pdb2v0 g1 io77pdb4v0 io115pdb4v0 g2 gnd gnd g3 io78ndb4v0 io116ndb4v0 g4 io78pdb4v0 io116pdb4v0 g5 vccib4 vccib4 g6 nc io117pdb4v0 g7 vccib4 vccib4 g8 gnd gnd g9 io04ndb0v0 io06ndb0v1 g10 io04pdb0v0 io06pdb0v1 g11 io12ndb0v1 io16ndb0v2 g12 io12pdb0v1 io16pdb0v2 g13 nc io28ndb1v1 g14 nc io28pdb1v1 g15 gnd gnd g16 nc io38ppb1v2 g17 nc io53pdb2v0 g18 vccib2 vccib2 g19 io36pdb2v0 io52pdb2v0 g20 io36ndb2v0 io52ndb2v0 g21 gnd gnd g22 io35ndb2v0 io51ndb2v0 h1 io77ndb4v0 io115ndb4v0 h2 io76pdb4v0 io113pdb4v0 h3 vccib4 vccib4 h4 io79ndb4v0 io114ndb4v0 h5 io79pdb4v0 io114pdb4v0 h6 nc io117ndb4v0 h7 gnd gnd h8 vcc vcc h9 vccib0 vccib0 h10 gnd gnd h11 vccib0 vccib0 h12 vccib1 vccib1 fg484 pin number afs600 function afs1500 function
fusion family of mixed signal fpgas revision 4 4-23 h13 gnd gnd h14 vccib1 vccib1 h15 gnd gnd h16 gnd gnd h17 nc io53ndb2v0 h18 io38pdb2v0 io57pdb2v0 h19 gca2/io39pdb2v 0 gca2/io59pdb2v0 h20 vccib2 vccib2 h21 io37ndb2v0 io54ndb2v0 h22 io37pdb2v0 io54pdb2v0 j1 nc io112ppb4v0 j2 io76ndb4v0 io113ndb4v0 j3 gfb2/io74pdb4v0 gfb2/io109pdb4v0 j4 gfa2/io75pdb4v0 gfa2/io110pdb4v0 j5 nc io112npb4v0 j6 nc io104pdb4v0 j7 nc io111pdb4v0 j8 vccib4 vccib4 j9 gnd gnd j10 vcc vcc j11 gnd gnd j12 vcc vcc j13 gnd gnd j14 vcc vcc j15 vccib2 vccib2 j16 gcb2/io40pdb2v0 gcb2/io60pdb2v0 j17 nc io58ndb2v0 j18 io38ndb2v0 io57ndb2v0 j19 io39ndb2v0 io59ndb2v0 j20 gcc2/io41pdb2v0 gcc2/io61pdb2v0 j21 nc io55psb2v0 j22 io42pdb2v0 io56pdb2v0 k1 gfc2/io73pdb4v0 g fc2/io108pdb4v0 k2 gnd gnd k3 io74ndb4v0 io109ndb4v0 fg484 pin number afs600 function afs1500 function k4 io75ndb4v0 io110ndb4v0 k5 gnd gnd k6 nc io104ndb4v0 k7 nc io111ndb4v0 k8 gnd gnd k9 vcc vcc k10 gnd gnd k11 vcc vcc k12 gnd gnd k13 vcc vcc k14 gnd gnd k15 gnd gnd k16 io40ndb2v0 io60ndb2v0 k17 nc io58pdb2v0 k18 gnd gnd k19 nc io68npb2v0 k20 io41ndb2v0 io61ndb2v0 k21 gnd gnd k22 io42ndb2v0 io56ndb2v0 l1 io73ndb4v0 io108ndb4v0 l2 vccosc vccosc l3 vccib4 vccib4 l4 xtal2 xtal2 l5 gfc1/io72pdb4v0 gfc1/io107pdb4v0 l6 vccib4 vccib4 l7 gfb1/io71pdb4v0 g fb1/io106pdb4v0 l8 vccib4 vccib4 l9 gnd gnd l10 vcc vcc l11 gnd gnd l12 vcc vcc l13 gnd gnd l14 vcc vcc l15 vccib2 vccib2 l16 io48pdb2v0 io70pdb2v0 fg484 pin number afs600 function afs1500 function
package pin assignments 4-24 revision 4 l17 vccib2 vccib2 l18 io46pdb2v0 io69pdb2v0 l19 gca1/io45pdb2v0 gca1/io64pdb2v0 l20 vccib2 vccib2 l21 gcc0/io43ndb2v0 gcc0/io62ndb2v0 l22 gcc1/io43pdb2v0 gcc1/io62pdb2v0 m1 nc io103pdb4v0 m2 xtal1 xtal1 m3 vccib4 vccib4 m4 gndosc gndosc m5 gfc0/io72ndb4v0 gfc0/io107ndb4v0 m6 vccib4 vccib4 m7 gfb0/io71ndb4v0 gfb0/io106ndb4v0 m8 vccib4 vccib4 m9 vcc vcc m10 gnd gnd m11 vcc vcc m12 gnd gnd m13 vcc vcc m14 gnd gnd m15 vccib2 vccib2 m16 io48ndb2v0 io70ndb2v0 m17 vccib2 vccib2 m18 io46ndb2v0 io69ndb2v0 m19 gca0/io45ndb2v0 gca0/io64ndb2v0 m20 vccib2 vccib2 m21 gcb0/io44ndb2v0 gcb0/io63ndb2v0 m22 gcb1/io44pdb2v0 gcb1/io63pdb2v0 n1 nc io103ndb4v0 n2 gnd gnd n3 io68pdb4v0 io101pdb4v0 n4 nc io100npb4v0 n5 gnd gnd n6 nc io99pdb4v0 n7 nc io97pdb4v0 fg484 pin number afs600 function afs1500 function n8 gnd gnd n9 gnd gnd n10 vcc vcc n11 gnd gnd n12 vcc vcc n13 gnd gnd n14 vcc vcc n15 gnd gnd n16 gdb2/io56pdb2v0 gdb2/io83pdb2v0 n17 nc io78pdb2v0 n18 gnd gnd n19 io47ndb2v0 io72ndb2v0 n20 io47pdb2v0 io72pdb2v0 n21 gnd gnd n22 io49pdb2v0 io71pdb2v0 p1 gfa1/io70pdb4v0 gfa1/io105pdb4v0 p2 gfa0/io70ndb4v0 gfa0/io105ndb4v0 p3 io68ndb4v0 io101ndb4v0 p4 io65pdb4v0 io96pdb4v0 p5 io65ndb4v0 io96ndb4v0 p6 nc io99ndb4v0 p7 nc io97ndb4v0 p8 vccib4 vccib4 p9 vcc vcc p10 gnd gnd p11 vcc vcc p12 gnd gnd p13 vcc vcc p14 gnd gnd p15 vccib2 vccib2 p16 io56ndb2v0 io83ndb2v0 p17 nc io78ndb2v0 p18 gda1/io54pdb2v0 gda1/io81pdb2v0 p19 gdb1/io53pdb2v0 gdb1/io80pdb2v0 p20 io51ndb2v0 io73ndb2v0 fg484 pin number afs600 function afs1500 function
fusion family of mixed signal fpgas revision 4 4-25 p21 io51pdb2v0 io73pdb2v0 p22 io49ndb2v0 io71ndb2v0 r1 io69pdb4v0 io102pdb4v0 r2 io69ndb4v0 io102ndb4v0 r3 vccib4 vccib4 r4 io64pdb4v0 io91pdb4v0 r5 io64ndb4v0 io91ndb4v0 r6 nc io92pdb4v0 r7 gnd gnd r8 gnd gnd r9 vcc33a vcc33a r10 gnda gnda r11 vcc33a vcc33a r12 gnda gnda r13 vcc33a vcc33a r14 gnda gnda r15 vcc vcc r16 gnd gnd r17 nc io74ndb2v0 r18 gda0/io54ndb2v0 gda0/io81ndb2v0 r19 gdb0/io53ndb2v0 gdb0/io80ndb2v0 r20 vccib2 vccib2 r21 io50ndb2v0 io75ndb2v0 r22 io50pdb2v0 io75pdb2v0 t1 nc io100ppb4v0 t2 gnd gnd t3 io66pdb4v0 io95pdb4v0 t4 io66ndb4v0 io95ndb4v0 t5 vccib4 vccib4 t6 nc io92ndb4v0 t7 gndnvm gndnvm t8 gnda gnda t9 nc nc t10 av4 av4 t11 nc nc fg484 pin number afs600 function afs1500 function t12 av5 av5 t13 ac5 ac5 t14 nc nc t15 gnda gnda t16 nc io77ppb2v0 t17 nc io74pdb2v0 t18 vccib2 vccib2 t19 io55ndb2v0 io82ndb2v0 t20 gda2/io55pdb2v0 gda2/io82pdb2v0 t21 gnd gnd t22 gdc1/io52pdb2v0 gdc1/io79pdb2v0 u1 io67pdb4v0 io98pdb4v0 u2 io67ndb4v0 io98ndb4v0 u3 gec1/io63pdb4v0 gec1/io90pdb4v0 u4 gec0/io63ndb4v0 gec0/io90ndb4v0 u5 gnd gnd u6 vccnvm vccnvm u7 vccib4 vccib4 u8 vcc15a vcc15a u9 gnda gnda u10 ac4 ac4 u11 vcc33a vcc33a u12 gnda gnda u13 ag5 ag5 u14 gnda gnda u15 pub pub u16 vccib2 vccib2 u17 tdi tdi u18 gnd gnd u19 io57ndb2v0 io84ndb2v0 u20 gdc2/io57pdb2v0 gdc2/io84pdb2v0 u21 nc io77npb2v0 u22 gdc0/io52ndb2v0 gdc0/io79ndb2v0 v1 geb1/io62pdb4v0 geb1/io89pdb4v0 v2 geb0/io62ndb4v 0 geb0/io89ndb4v0 fg484 pin number afs600 function afs1500 function
package pin assignments 4-26 revision 4 v3 vccib4 vccib4 v4 gea1/io61pdb4v0 gea1/io88pdb4v0 v5 gea0/io61ndb4v0 gea0/io88ndb4v0 v6 gnd gnd v7 vcc33pmp vcc33pmp v8 nc nc v9 vcc33a vcc33a v10 ag4 ag4 v11 at4 at4 v12 atrtn2 atrtn2 v13 at5 at5 v14 vcc33a vcc33a v15 nc nc v16 vcc33a vcc33a v17 gnd gnd v18 tms tms v19 vjtag vjtag v20 vccib2 vccib2 v21 trst trst v22 tdo tdo w1 nc io93pdb4v0 w2 gnd gnd w3 nc io93ndb4v0 w4 geb2/io59pdb4v0 geb2/io86pdb4v0 w5 io59ndb4v0 io86ndb4v0 w6 av0 av0 w7 gnda gnda w8 av1 av1 w9 av2 av2 w10 gnda gnda w11 av3 av3 w12 av6 av6 w13 gnda gnda w14 av7 av7 w15 av8 av8 fg484 pin number afs600 function afs1500 function w16 gnda gnda w17 av9 av9 w18 vccib2 vccib2 w19 nc io68ppb2v0 w20 tck tck w21 gnd gnd w22 nc io76ppb2v0 y1 gec2/io60pdb4v0 gec2/io87pdb4v0 y2 io60ndb4v0 io87ndb4v0 y3 gea2/io58pdb4v0 gea2/io85pdb4v0 y4 io58ndb4v0 io85ndb4v0 y5 ncap ncap y6 ac0 ac0 y7 vcc33a vcc33a y8 ac1 ac1 y9 ac2 ac2 y10 vcc33a vcc33a y11 ac3 ac3 y12 ac6 ac6 y13 vcc33a vcc33a y14 ac7 ac7 y15 ac8 ac8 y16 vcc33a vcc33a y17 ac9 ac9 y18 adcgndref adcgndref y19 ptbase ptbase y20 gndnvm gndnvm y21 vccnvm vccnvm y22 vpump vpump fg484 pin number afs600 function afs1500 function
fusion family of mixed signal fpgas revision 4 4-27 fg676 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/default.aspx . a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
package pin assignments 4-28 revision 4 fg676 pin number afs1500 function a1 nc a2 gnd a3 nc a4 nc a5 gnd a6 nc a7 nc a8 gnd a9 io17ndb0v2 a10 io17pdb0v2 a11 gnd a12 io18ndb0v2 a13 io18pdb0v2 a14 io20ndb0v2 a15 io20pdb0v2 a16 gnd a17 io21pdb0v2 a18 io21ndb0v2 a19 gnd a20 io39ndb1v2 a21 io39pdb1v2 a22 gnd a23 nc a24 nc a25 gnd a26 nc aa1 nc aa2 vccib4 aa3 io93pdb4v0 aa4 gnd aa5 io93ndb4v0 aa6 geb2/io86pdb4v0 aa7 io86ndb4v0 aa8 av0 aa9 gnda aa10 av1 aa11 av2 aa12 gnda aa13 av3 aa14 av6 aa15 gnda aa16 av7 aa17 av8 aa18 gnda aa19 av9 aa20 vccib2 aa21 io68ppb2v0 aa22 tck aa23 gnd aa24 io76ppb2v0 aa25 vccib2 aa26 nc ab1 gnd ab2 nc ab3 gec2/io87pdb4v0 ab4 io87ndb4v0 ab5 gea2/io85pdb4v0 ab6 io85ndb4v0 ab7 ncap ab8 ac0 ab9 vcc33a ab10 ac1 ab11 ac2 ab12 vcc33a ab13 ac3 ab14 ac6 ab15 vcc33a ab16 ac7 ab17 ac8 ab18 vcc33a ab19 ac9 ab20 adcgndref fg676 pin number afs1500 function ab21 ptbase ab22 gndnvm ab23 vccnvm ab24 vpump ab25 nc ab26 gnd ac1 nc ac2 nc ac3 nc ac4 gnd ac5 vccib4 ac6 vccib4 ac7 pcap ac8 ag0 ac9 gnda ac10 ag1 ac11 ag2 ac12 gnda ac13 ag3 ac14 ag6 ac15 gnda ac16 ag7 ac17 ag8 ac18 gnda ac19 ag9 ac20 varef ac21 vccib2 ac22 ptem ac23 gnd ac24 nc ac25 nc ac26 nc ad1 nc ad2 nc ad3 gnd ad4 nc fg676 pin number afs1500 function
fusion family of mixed signal fpgas revision 4 4-29 ad5 io94npb4v0 ad6 gnd ad7 vcc33n ad8 at0 ad9 atrtn0 ad10 at1 ad11 at2 ad12 atrtn1 ad13 at3 ad14 at6 ad15 atrtn3 ad16 at7 ad17 at8 ad18 atrtn4 ad19 at9 ad20 vcc33a ad21 gnd ad22 io76npb2v0 ad23 nc ad24 gnd ad25 nc ad26 nc ae1 gnd ae2 gnd ae3 nc ae4 nc ae5 nc ae6 nc ae7 nc ae8 nc ae9 gnda ae10 nc ae11 nc ae12 gnda ae13 nc ae14 nc fg676 pin number afs1500 function ae15 gnda ae16 nc ae17 nc ae18 gnda ae19 nc ae20 nc ae21 nc ae22 nc ae23 nc ae24 nc ae25 gnd ae26 gnd af1 nc af2 gnd af3 nc af4 nc af5 nc af6 nc af7 nc af8 nc af9 vcc33a af10 nc af11 nc af12 vcc33a af13 nc af14 nc af15 vcc33a af16 nc af17 nc af18 vcc33a af19 nc af20 nc af21 nc af22 nc af23 nc af24 nc fg676 pin number afs1500 function af25 gnd af26 nc b1 gnd b2 gnd b3 nc b4 nc b5 nc b6 vccib0 b7 nc b8 nc b9 vccib0 b10 io15ndb0v2 b11 io15pdb0v2 b12 vccib0 b13 io19ndb0v2 b14 io19pdb0v2 b15 vccib1 b16 io25ndb1v0 b17 io25pdb1v0 b18 vccib1 b19 io33ndb1v1 b20 io33pdb1v1 b21 vccib1 b22 nc b23 nc b24 nc b25 gnd b26 gnd c1 nc c2 nc c3 gnd c4 nc c5 gaa1/io01pdb0v0 c6 gab0/io02ndb0v0 c7 gab1/io02pdb0v0 c8 io07ndb0v1 fg676 pin number afs1500 function
package pin assignments 4-30 revision 4 c9 io07pdb0v1 c10 io09pdb0v1 c11 io13ndb0v2 c12 io13pdb0v2 c13 io24pdb1v0 c14 io26pdb1v0 c15 io27ndb1v1 c16 io27pdb1v1 c17 io35ndb1v2 c18 io35pdb1v2 c19 gbc0/io40ndb1v2 c20 gba0/io42ndb1v2 c21 io43ndb1v2 c22 io43pdb1v2 c23 nc c24 gnd c25 nc c26 nc d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io01ndb0v0 d6 gnd d7 io04ndb0v0 d8 io04pdb0v0 d9 gnd d10 io09ndb0v1 d11 io11pdb0v1 d12 gnd d13 io24ndb1v0 d14 io26ndb1v0 d15 gnd d16 io31ndb1v1 d17 io31pdb1v1 d18 gnd fg676 pin number afs1500 function d19 gbc1/io40pdb1v2 d20 gba1/io42pdb1v2 d21 gnd d22 vccplb d23 gnd d24 nc d25 nc d26 nc e1 gnd e2 io122npb4v0 e3 io121pdb4v0 e4 io122ppb4v0 e5 io00ndb0v0 e6 io00pdb0v0 e7 vccib0 e8 io05ndb0v1 e9 io05pdb0v1 e10 vccib0 e11 io11ndb0v1 e12 io14pdb0v2 e13 vccib0 e14 vccib1 e15 io29ndb1v1 e16 io29pdb1v1 e17 vccib1 e18 io37ndb1v2 e19 gbb0/io41ndb1v2 e20 vccib1 e21 vcomplb e22 gba2/io44pdb2v0 e23 io48ppb2v0 e24 gbb2/io45pdb2v0 e25 nc e26 gnd f1 nc f2 vccib4 fg676 pin number afs1500 function f3 io121ndb4v0 f4 gnd f5 io123ndb4v0 f6 gac2/io123pdb4v0 f7 gaa2/io125pdb4v0 f8 gac0/io03ndb0v0 f9 gac1/io03pdb0v0 f10 io10ndb0v1 f11 io10pdb0v1 f12 io14ndb0v2 f13 io23ndb1v0 f14 io23pdb1v0 f15 io32npb1v1 f16 io34ndb1v1 f17 io34pdb1v1 f18 io37pdb1v2 f19 gbb1/io41pdb1v2 f20 vccib2 f21 io47ppb2v0 f22 io44ndb2v0 f23 gnd f24 io45ndb2v0 f25 vccib2 f26 nc g1 nc g2 io119ppb4v0 g3 io120ndb4v0 g4 io120pdb4v0 g5 vccib4 g6 gab2/io124pdb4v0 g7 io125ndb4v0 g8 gnd g9 vccib0 g10 io08ndb0v1 g11 io08pdb0v1 g12 gnd fg676 pin number afs1500 function
fusion family of mixed signal fpgas revision 4 4-31 g13 io22ndb1v0 g14 io22pdb1v0 g15 gnd g16 io32ppb1v1 g17 io36npb1v2 g18 vccib1 g19 gnd g20 io47npb2v0 g21 io49pdb2v0 g22 vccib2 g23 io46ndb2v0 g24 gbc2/io46pdb2v0 g25 io48npb2v0 g26 nc h1 gnd h2 nc h3 io118ndb4v0 h4 io118pdb4v0 h5 io119npb4v0 h6 io124ndb4v0 h7 gnd h8 vcompla h9 vccpla h10 vccib0 h11 io12ndb0v1 h12 io12pdb0v1 h13 vccib0 h14 vccib1 h15 io30ndb1v1 h16 io30pdb1v1 h17 vccib1 h18 io36ppb1v2 h19 io38npb1v2 h20 gnd h21 io49ndb2v0 h22 io50pdb2v0 fg676 pin number afs1500 function h23 io50ndb2v0 h24 io51pdb2v0 h25 nc h26 gnd j1 nc j2 vccib4 j3 io115pdb4v0 j4 gnd j5 io116ndb4v0 j6 io116pdb4v0 j7 vccib4 j8 io117pdb4v0 j9 vccib4 j10 gnd j11 io06ndb0v1 j12 io06pdb0v1 j13 io16ndb0v2 j14 io16pdb0v2 j15 io28ndb1v1 j16 io28pdb1v1 j17 gnd j18 io38ppb1v2 j19 io53pdb2v0 j20 vccib2 j21 io52pdb2v0 j22 io52ndb2v0 j23 gnd j24 io51ndb2v0 j25 vccib2 j26 nc k1 nc k2 nc k3 io115ndb4v0 k4 io113pdb4v0 k5 vccib4 k6 io114ndb4v0 fg676 pin number afs1500 function k7 io114pdb4v0 k8 io117ndb4v0 k9 gnd k10 vcc k11 vccib0 k12 gnd k13 vccib0 k14 vccib1 k15 gnd k16 vccib1 k17 gnd k18 gnd k19 io53ndb2v0 k20 io57pdb2v0 k21 gca2/io59pdb2v0 k22 vccib2 k23 io54ndb2v0 k24 io54pdb2v0 k25 nc k26 nc l1 gnd l2 nc l3 io112ppb4v0 l4 io113ndb4v0 l5 gfb2/io109pdb4v0 l6 gfa2/io110pdb4v0 l7 io112npb4v0 l8 io104pdb4v0 l9 io111pdb4v0 l10 vccib4 l11 gnd l12 vcc l13 gnd l14 vcc l15 gnd l16 vcc fg676 pin number afs1500 function
package pin assignments 4-32 revision 4 l17 vccib2 l18 gcb2/io60pdb2v0 l19 io58ndb2v0 l20 io57ndb2v0 l21 io59ndb2v0 l22 gcc2/io61pdb2v0 l23 io55ppb2v0 l24 io56pdb2v0 l25 io55npb2v0 l26 gnd m1 nc m2 vccib4 m3 gfc2/io108pdb4v0 m4 gnd m5 io109ndb4v0 m6 io110ndb4v0 m7 gnd m8 io104ndb4v0 m9 io111ndb4v0 m10 gnd m11 v cc m12 gnd m13 vcc m14 gnd m15 vcc m16 gnd m17 gnd m18 io60ndb2v0 m19 io58pdb2v0 m20 gnd m21 io68npb2v0 m22 io61ndb2v0 m23 gnd m24 io56ndb2v0 m25 vccib2 m26 io65pdb2v0 fg676 pin number afs1500 function n1 nc n2 nc n3 io108ndb4v0 n4 vccosc n5 vccib4 n6 xtal2 n7 gfc1/io107pdb4v0 n8 vccib4 n9 gfb1/io106pdb4v0 n10 vccib4 n11 gnd n12 vcc n13 gnd n14 vcc n15 gnd n16 vcc n17 vccib2 n18 io70pdb2v0 n19 vccib2 n20 io69pdb2v0 n21 gca1/io64pdb2v0 n22 vccib2 n23 gcc0/io62ndb2v0 n24 gcc1/io62pdb2v0 n25 io66pdb2v0 n26 io65ndb2v0 p1 nc p2 nc p3 io103pdb4v0 p4 xtal1 p5 vccib4 p6 gndosc p7 gfc0/io107ndb4v0 p8 vccib4 p9 gfb0/io106ndb4v0 p10 vccib4 fg676 pin number afs1500 function p11 vcc p12 gnd p13 vcc p14 gnd p15 vcc p16 gnd p17 vccib2 p18 io70ndb2v0 p19 vccib2 p20 io69ndb2v0 p21 gca0/io64ndb2v0 p22 vccib2 p23 gcb0/io63ndb2v0 p24 gcb1/io63pdb2v0 p25 io66ndb2v0 p26 io67pdb2v0 r1 nc r2 vccib4 r3 io103ndb4v0 r4 gnd r5 io101pdb4v0 r6 io100npb4v0 r7 gnd r8 io99pdb4v0 r9 io97pdb4v0 r10 gnd r11 gnd r12 vcc r13 gnd r14 vcc r15 gnd r16 vcc r17 gnd r18 gdb2/io83pdb2v0 r19 io78pdb2v0 r20 gnd fg676 pin number afs1500 function
fusion family of mixed signal fpgas revision 4 4-33 r21 io72ndb2v0 r22 io72pdb2v0 r23 gnd r24 io71pdb2v0 r25 vccib2 r26 io67ndb2v0 t1 gnd t2 nc t3 gfa1/io105pdb4v0 t4 gfa0/io105ndb4v0 t5 io101ndb4v0 t6 io96pdb4v0 t7 io96ndb4v0 t8 io99ndb4v0 t9 io97ndb4v0 t10 vccib4 t11 vcc t12 gnd t13 vcc t14 gnd t15 vcc t16 gnd t17 vccib2 t18 io83ndb2v0 t19 io78ndb2v0 t20 gda1/io81pdb2v0 t21 gdb1/io80pdb2v0 t22 io73ndb2v0 t23 io73pdb2v0 t24 io71ndb2v0 t25 nc t26 gnd u1 nc u2 nc u3 io102pdb4v0 u4 io102ndb4v0 fg676 pin number afs1500 function u5 vccib4 u6 io91pdb4v0 u7 io91ndb4v0 u8 io92pdb4v0 u9 gnd u10 gnd u11 vcc33a u12 gnda u13 vcc33a u14 gnda u15 vcc33a u16 gnda u17 vcc u18 gnd u19 io74ndb2v0 u20 gda0/io81ndb2v0 u21 gdb0/io80ndb2v0 u22 vccib2 u23 io75ndb2v0 u24 io75pdb2v0 u25 nc u26 nc v1 nc v2 vccib4 v3 io100ppb4v0 v4 gnd v5 io95pdb4v0 v6 io95ndb4v0 v7 vccib4 v8 io92ndb4v0 v9 gndnvm v10 gnda v11 nc v12 av4 v13 nc v14 av5 fg676 pin number afs1500 function v15 ac5 v16 nc v17 gnda v18 io77ppb2v0 v19 io74pdb2v0 v20 vccib2 v21 io82ndb2v0 v22 gda2/io82pdb2v0 v23 gnd v24 gdc1/io79pdb2v0 v25 vccib2 v26 nc w1 gnd w2 io94ppb4v0 w3 io98pdb4v0 w4 io98ndb4v0 w5 gec1/io90pdb4v0 w6 gec0/io90ndb4v0 w7 gnd w8 vccnvm w9 vccib4 w10 vcc15a w11 gnda w12 ac4 w13 vcc33a w14 gnda w15 ag5 w16 gnda w17 pub w18 vccib2 w19 tdi w20 gnd w21 io84ndb2v0 w22 gdc2/io84pdb2v0 w23 io77npb2v0 w24 gdc0/io79ndb2v0 fg676 pin number afs1500 function
package pin assignments 4-34 revision 4 w25 nc w26 gnd y1 nc y2 nc y3 geb1/io89pdb4v0 y4 geb0/io89ndb4v0 y5 vccib4 y6 gea1/io88pdb4v0 y7 gea0/io88ndb4v0 y8 gnd y9 vcc33pmp y10 nc y11 vcc33a y12 ag4 y13 at4 y14 atrtn2 y15 at5 y16 vcc33a y17 nc y18 vcc33a y19 gnd y20 tms y21 vjtag y22 vccib2 y23 trst y24 tdo y25 nc y26 nc fg676 pin number afs1500 function
revision 4 5-1 5 ? datasheet information list of changes the following table lists critical changes that were made in each revision of the fusion datasheet. revision changes page revision 4 (january 2013) the "product ordering codes" section has been updated to mention "y" as "blank" mentioning "device does not include license to implement ip based on the cryptography research, inc. (cri) patent portfolio" (sar 43177). iii the note in table 2-12 ? fusion ccc/pll specification referring the reader to smartgen was revised to refer instead to the online help associated with the core (sar 42563). 2-30 table 2-49 ? analog channel specifications was modified to update the uncalibrated offset values (afs250) of the external and internal temperature monitors (sar 43134). 2-120 in table 2-57 ? prescaler control truth table?av (x = 0), ac (x = 1), and at (x = 3) , changed the column heading from 'full-scale voltage' to 'full scale voltage in 10-bit mode', and added and updated notes as required (sar 20812). 2-133 the values for the speed grade (-1 and std.) for fddrimax ( table 2-180 ? input ddr propagation delays ) and values for the speed grade (-2 and std.) for fddomax ( table 2-182 ? output ddr propagation delays ) had been inadvertently interchanged. this has been rectified (sar 38514). 2-223 , 2-225 added description about what happens if a user connects varef to an external 3.3 v on their board to the "varef analog reference voltage" section (sar 35188). 2-228 added a note to table 3-2 ? recommended operating conditions1 (sar 43429): the programming temperature range supported is t ambient = 0c to 85c. 3-3 added the package thermal details for afs600-pq208 and afs250-pq208 to table 3-6 ? package thermal resistance (sar 37816). deleted the die size column from the table (sar 43503). 3-7 libero integrated design environment (ide) was changed to libero system-on-chip (soc) throughout the document (sar 42495). live at power-up (lapu) has been replaced with ?instant on?. na revision 3 (august 2012) microblade u1afs250 and u1afs1500 devices were added to the product tables. i ? iv a sentence pertaining to the analog i/os was added to the "specifying i/o states during programming" section (sar 34831). 1-8 the "rc oscillator" section was revised to correct a sentence that did not differentiate accuracy for commercial and industrial temperature ranges, which is given in table 2-9 ? electrical characteristics of rc oscillator (sar 33722). 2-20 figure 2-57 ? fifo read and figure 2-58 ? fifo write are new (sar 34840). 2-75 the first paragraph of the "offset" section was removed; it was intended to be replaced by the paragraph following it (sar 22647). 2-98 iol and ioh values for 3.3 v gtl+ and 2.5 v gtl+ were corrected in table 2-86 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions (sar 39813). 2-167
datasheet information 5-2 revision 4 revision 3 (continued) the drive strength, iol, and ioh for 3.3 v gtl and 2.5 v gtl were changed from 25 ma to 20 ma in the following tables (sar 37373): table 2-86 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions , table 2-92 ? summary of i/o timing characteristics ? software default settings table 2-96 ? i/o output buffer maximum resistances 1 table 2-138 ? minimum and maximum dc input and output levels table 2-141 ? minimum and maximum dc input and output levels 2-167 2-170 2-172 2-202 2-203 the following sentence was deleted from the "2.5 v lvcmos" section (sar 34800): "it uses a 5 v?tolerant input buffer and push-pull output buffer." 2-184 corrected the inadvertent e rror in maximum values for lvpecl vih and vil and revised them to "3.6" in table 2-171 ? minimum and maximum dc input and output levels , making these consistent with table 3-1 ? absolute maximum ratings , and table 3-4 ? overshoot and undershoot limits 1 (sar 37687). 2-214 the maximum frequency for global clock parameter was removed from ta b l e 2 - 5 ? afs1500 global resource timing through table 2-8 ? afs090 global resource timing because a frequency on the global is only an indication of what the global network can do. there are other limiter s such as the sram, i/os, and pll. smarttime software should be used to determine the design frequency (sar 36955). 2-17 to 2-18 revision 2 (march 2012) the phrase "without debug" was removed from the "soft arm cortex-m1 fusion devices (m1)" section (sar 21390). i the "in-system programming (isp) and security" section , "security" section , "flash advantages" section , and "security" section were revised to clarify that although no existing security measures can give an absolute guarantee, microsemi fpgas implement the best security availa ble in the industry (sar 34679). i , 1-2 , 2-231 the y security option and licensed dpa logo was added to the "product ordering codes" section . the trademarked licensed dpa logo identifies that a product is covered by a dpa counter-measures lic ense from cryptography research (sar 34721). iii the "specifying i/o states during programming" section is new (sar 34693). 1-8 the following information was added before figure 2-17 ? xtlosc macro : in the case where the crystal oscillator block is not used, the xtal1 pin should be connected to gnd and the xtal2 pin should be left floating (sar 24119). 2-21 table 2-12 ? fusion ccc/pll specification was updated. a note was added indicating that when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available (sar 34814). 2-30 a note was added to figure 2-27 ? real-time counter s ystem (not all the signals are shown for the ab macro) stating that the user is only required to instantiate the vrpsm macro if the user wishes to spec ify pupo behavior of the voltage regulator to be different from the default, or employ user logic to shut the voltage regulator off (sar 21773). 2-33 revision changes page
fusion family of mixed signal fpgas revision 4 5-3 revision 2 (continued) vpump was incorrectly represented as vpp in several places. this was corrected to vpump in the "standby and sleep mode circuit implementation" section and table 3-8 ? afs1500 quiescent supply current characteristics through table 3-11 ? afs090 quiescent supply current characteristics (21963). 2-34 , 3-10 additional information was added to the flash memory block "write operation" section , including an explanation of the fact that a copy-page operation takes no less than 55 cycles (sar 26338). 2-47 the "flashrom" section was revised to refer to figure 2-46 ? flashrom timing diagram and table 2-26 ? flashrom access time rather than stating 20 mhz as the maximum flashrom access clock and 10 ns as the time interval for d0 to become valid or invalid (sar 22105). 2-56 , 2-57 the following figures were deleted (sar 29991). reference was made to a new application note, simultaneous read-write operations in dual-port sram for flash- based csocs and fpga s , which covers these cases in detail (sar 34862). figure 2-55 ? write access after write onto same address figure 2-56 ? read access after write onto same address figure 2-57 ? write access after read onto same address the port names in the sram "timing waveforms" , "timing characteristics" , sram tables, figure 2-55 ? ram reset. applicable to both ram4k9 and ram512x18. , and the fifo "timing characteristics" tables were revised to ensure consistency with the software names (sar 35753). 2-66 , 2-69 , 2-68 , 2-78 in several places throughout the datasheet, gndref was corrected to adcgndref (sar 20783): figure 2-64 ? analog block macro table 2-36 ? analog block pin description "adc operation" section 2-80 2-81 2-107 the following note was added below figure 2-78 ? timing diagram for the temperature monitor strobe signal : when the ieee 1149.1 boundary scan extest instruction is exec uted, the ag pad drive strength ceases and becomes a 1 a sink into the fusion device. (sar 24796). 2-96 the "analog-to-digital converter block" section was extensively revised, reorganizing the information and adding the "adc theory of operation" section and "acquisition time or samp le time control" section . the "adc example" section was reworked and corrected (sar 20577). 2-99 table 2-49 ? analog channel specifications was modified to include calibrated and uncalibrated values for offset (afs090 a nd afs250) for the external and internal temperature monitors. the "offset" section was revised accordingly and now references table 2-49 ? analog channel specifications (sars 22647, 27015). 2-98 , 2-120 the "intra-conversion" section and "injected conversion" section had definitions incorrectly interchanged and have been corrected. figure 2-92 ? intra-conversion timing diagram and figure 2-93 ? injected conversion timing diagram were also incorrectly interchanged and have been replaced correctly. reference in the figure notes to eq 10 has been corrected to eq 23 (sar 20547). 2-112 , 2-115 , 2-116 the prescalar range for the 'analog input (d irect input to adc)" configurations was removed as inapplicable for direct inputs. the input resistance for direct inputs is covered in table 2-50 ? adc characteristics in direct input mode (sar 31201). 2-123 revision changes page
datasheet information 5-4 revision 4 revision 2 (continued) the "examples" for calibrating accuracy for adc channels were revised and corrected to make them consistent with terminology in the associated tables (sars 36791, 36773). 2-127 a note was added to table 2-56 ? analog quad acm byte assignment and the introductory text for table 2-66 ? internal temperature monitor control truth table , stating that for the internal temperature moni tor to function, bit 0 of byte 2 for all 10 quads must be set (sar 34418). 2-132 , 2-134 t dout was corrected to t din in figure 2-116 ? input buffer timing model and delays (example) (sar 37115). 2-164 the formulas in the table notes for table 2-97 ? i/o weak pull-up/pull-down resistances were corrected (sar 34751). 2-174 the ac loading figures in the "single-ended i/o characteristics" section were updated to match tables in the "summary of i/o timing characteristics ? default i/o software settings" section (sar 34877). 2-178 the following notes were removed from table 2-168 ? minimum and maximum dc input and output levels (sar 34808): 5% differential input voltage = 350 mv 2-212 an incomplete, duplicate sentence was removed from the end of the "gndaq ground (analog quiet)" pin description (sar 30185). 2-226 information about configuration of unused i/os was added to the "user pins" section (sar 32642). 2-228 the following information was added to the pin description for "xtal1 crystal oscillator circuit input" and "xtal2 crystal oscillator circuit input" (sar 24119). 2-230 the input resistance to ground value in table 3-3 ? input resistance of analog pads for analog input (direct input to adc), was corrected from 1 m ? (typical) to 2 k ? (typical) (sar 34371). 3-4 the storage temperature column in table 3-5 ? fpga programming, storage, and operating limits stated min. t j twice for commercial and industrial product grades and has been corrected to min. t j and max. t j (sar 29416). 3-5 the reference to guidelines for global spines and versatile rows, given in the "global clock dynamic contribution?pclock" section , was corrected to t he "spine architecture" section of the global resources chapter in the fusion fpga fabric user's guide (sar 34741). 3-24 package names used in the "package pin assignments" section were revised to match standards given in package mechanical drawings (sar 36612). 4-1 july 2010 the versioning system for datasheets has been changed. datasheets are assigned a revision number that increments each time the datasheet is revised. the "fusion device status" table indicates the status for each device in the device family. n/a revision changes page
fusion family of mixed signal fpgas revision 4 5-5 v2.0, revision 1 (july 2009) the microblade and fusion datasheets have been combined. pigeon point information is new. coremp7 support was removed since it is no longer offered. ?f was removed from the datasheet since it is no longer offered. the operating temperature was changed from ambient to junction to better reflect actual conditions of operations. commercial: 0c to 85c industrial: ?40c to 100c the version number category was changed from preliminary to production, which means the datasheet contains information based on final characterization. the version number changed from preliminary v1.7 to v2.0. n/a the "integrated analog blocks and analog i/os" section was updated to include a reference to the "analog system characteristics " section in the device architecture chapter of the datasheet, which includes table 2-46 ? analog channel specifications and specific voltage data. 1-4 the phrase "commercial-case conditions" in timing table titles was changed to "commercial temperature range conditions." n/a the "crystal oscillator" section was updated significantly. please review carefully. 2-21 the "real-time counter (part of ab macro)" section was updated significantly. please review carefully. 2-35 there was a typo in table 2-19 ? flash memory block pin names for the erasepage description; it wa s the same as discardpage. as as a result, the erasepage description was updated. 2-42 the t fmaxclknvm parameter was updated in table 2-25 ? flash memory block timing . 2-54 table 2-31 ? ram4k9 and table 2-32 ? ram512x18 were updated. 2-69 in table 2-36 ? analog block pin description , the function description for pwrdwn was changed from "comparator power-down if 1" to "adc comparator power-down if 1. when asserted, the adc will stop functioning, and the digital portion of the analog block will continue operating. this may result in invalid status flags from the analog block. therefore, microsemi does not recommend asserting the pwrdwn pin." 2-81 figure 2-75 ? gate driver example was updated. 2-94 the "adc operation" section was updated. please review carefully. 2-107 figure 2-92 ? intra-conversion timing diagram and figure 2-93 ? injected conversion timing diagram are new. 2-116 the "typical performance ch aracteristics" section is new. 2-118 table 2-49 ? analog channel specifications was significantly updated. 2-120 table 2-50 ? adc characteristics in direct input mode was significantly updated. 2-123 in table 2-52 ? calibrated analog channel accuracy 1,2,3 , note 2 was updated. 2-126 in table 2-53 ? analog channel accuracy: monitoring standard positive voltages , note 1 was updated. 2-127 in table 2-54 ? acm address decode table for analog quad , bit 89 was removed. 2-129 revision changes page
datasheet information 5-6 revision 4 v2.0, revision 1 (continued) the data in the 2.5 v lcmos and lvcmos 2.5 v / 5.0 v rows were updated in table 2-75 ? fusion standard and advanced i/o ? hot-swap and 5 v input tolerance capabilities . 2-146 in table 2-78 ? fusion standard i/o standards?out_drive settings , lvcmos 1.5 v, for out_drive 2, was changed from a dash to a check mark. 2-155 the "vcc15a analog power supply (1.5 v)" definition was changed from "a 1.5 v analog power supply input should be used to provide this input" to "1.5 v clean analog power supply input for use by the 1. 5 v portion of the analog circuitry." 2-226 in the "vcc33pmp analog power supply (3.3 v)" pin description, the following text was changed from "vcc33pmp should be powered up before or simultaneously with vcc33a" to "vcc33pmp should be powered up simultaneously with or after vcc33a." 2-226 the "vccosc oscillator power supply (3.3 v)" section was updated to include information about when to power the pin. 2-227 in the "128-bit aes decryption" section , fips-192 was incorrect and changed to fips-197. 2-231 the note in table 2-84 ? fusion standard and advanced i/o attributes vs. i/o standard applications was updated. 2-159 for 1.5 v lvcmos, the vil and vih parameters, 0.30 * vcci was changed to 0.35 * vcci and 0.70 * vcci was changed to 0.65 * vcci in table 2-86 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions , table 2-87 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions , and table 2-88 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions . in table 2-87 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions , the vih max column was updated. 2-167 to 2-168 table 2-89 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions was updated to include notes 3 and 4. the temperature ranges were also updated in notes 1 and 2. 2-168 the titles in table 2-92 ? summary of i/o timing characteristics ? software default settings to table 2-94 ? summary of i/o timing characteristics ? software default settings were updated to "vcci = i/o standard dependent." 2-170 to 2-171 below table 2-98 ? i/o short currents iosh/iosl , the paragraph was updated to change 110c to 100c and three mo nths was changed to six months. 2-175 table 2-99 ? short current ev ent duration before failure was updated to remove 110c data. 2-177 in table 2-101 ? i/o input rise time, fall time, and related i/o reliability , lvttl/lvcmos rows were changed from 110c to 100c. 2-177 vcc33pmp was added to table 3-1 ? absolute maximum ratings . in addition, conditions for av, ac, ag, and at were also updated. 3-1 vcc33pmp was added to table 3-2 ? recommended operating conditions1 . in addition, conditions for av, ac, ag, and at were also updated. 3-3 table 3-5 ? fpga programming, storage, and operating limits was updated to include new data and the temperatur e ranges were changed. the notes were removed from the table. 3-5 revision changes page
fusion family of mixed signal fpgas revision 4 5-7 v2.0, revision 1 (continued) table 3-6 ? package thermal resistance was updated to include new data. 3-7 in eq 4 to eq 6 , the junction temperature was changed from 110c to 100c. 3-8 to 3-8 table 3-8 ? afs1500 quiescent supply current characteristics through table 3-11 ? afs090 quiescent supply current characteristics are new and have replaced the quiescent supply current ch aracteristics (iddq) table. 3-10 to 3-16 in table 3-14 ? different components contributing to the dynamic power consumption in fusion devices , the power supply for pac9 and pac10 were changed from vmv/vcc to vcci. 3-22 in table 3-15 ? different components contribu ting to the static power consumption in fusion devices , the power supply for pdc7 and pdc8 were changed from vmv/vcc to vcci. pdc1 was updated from tbd to 18. 3-23 the "qn108" table was updated to remove the duplicates of pins b12 and b34. 4-2 preliminary v1.7 (october 2008) the version number category was changed from advance to preliminary, which means the datasheet contains informati on based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. for the vil and vih parameters, 0.30 * vc ci was changed to 0.35 * vcci and 0.70 * vcci was changed to 0.65 * vcci in table 2-126 ? minimum and maximum dc input and output levels . 2-196 the version number category was changed from advance to preliminary, which means the datasheet contains informati on based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. n/a the following updates were made to table 2-141 ? minimum and maximum dc input and output levels : temperature digital output 213 00 1111 1101 283 01 0001 1011 358 01 0110 0110 ? only the digital output was updated. temperature 358 remains in the temperature column. 2-203 in advance v1.2, the "varef analog reference voltage" pin description was significantly updated but the change was not noted in the change table. 2-228 advance v1.6 (august 2008) the title of the datasheet changed from actel programmable system chips to actel fusion mixed signal fpgas. in addition, all instances of programmable system chip were changed to mixed signal fpga. n/a the references to the peripherals user?s guide in the "no-glitch mux (ngmux)" section and "voltage regulator power supply monitor (vrpsm)" section were changed to fusion handbook . 2-32 , 2-42 advance v1.5 (july 2008) the following bullet was updated from high-voltage input tolerance: 12 v to high- voltage input tolerance: 10.5 v to 12 v. i the following bullet was updated from prog rammable 1, 3, 10, 30 a and 25 ma drive strengths to programmable 1, 3, 10, 30 a and 20 ma drive strengths. i revision changes page
datasheet information 5-8 revision 4 advance v1.5 (continued) this bullet was added to the "integrated a/d converte r (adc) and analog i/o" section : adc accuracy is better than 1% i in the "integrated analog blocks and analog i/os" section , 4 lsb was changed to 0.72. the following sentence was deleted: the input range for voltage signals is fr om ?12 v to +12 v with full-scale output values from 0.125 v to 16 v. in addition, 2c was changed to 3c: "one analog input in each quad can be connected to an external temperature monitor diode and achieves detection accuracy of 3oc." the following sentence was deleted: the input range for voltage signals is fr om ?12 v to +12 v with full-scale output values from 0.125 v to 16 v. 1-4 the title of the datasheet changed from actel programmable system chips to actel fusion mixed signal fpgas. in addition, all instances of programmable system chip were changed to mixed signal fpga. n/a advance v1.4 (july 2008) in table 3-8 quiescent supply current characteristics (iddq)1 , footnote references were updated for i dc2 and i dc3 . footnote 3 and 4 were updated and footnote 5 is new. 3-11 advance v1.3 (july 2008) the "adc description" section was significantly updated. please review carefully. 2-102 advance v1.2 (may 2008) table 2-25 ? flash memory block timing was significantly updated. 2-55 the "v aref analog reference voltage" pin description sect ion was significantly update. please review it carefully. 2-226 table 2-45 ? adc interface timing was significantly updated. 2-110 table 2-56 ? direct analog input switch contro l truth table?av (x = 0), ac (x = 1), and at (x = 3) was significantly updated. 2-131 the following sentence was deleted from the "voltage monitor" section : the analog quad inputs are tolerant up to 12 v + 10%. 2-86 the "180-pin qfn" figure was updated. d1 to d4 are new and the figure was changed to bottom view. the note below the figure is new. 3-3 advance v1.1 (may 2008) the following text was incorrect and therefore deleted: vcc33a analog power filter analog power pin for the analog power supply low-pass filter. an external 100 pf capacitor should be connected between this pin and ground. there is still a description of v cc33a on page 2-224 . 2-204 revision changes page
fusion family of mixed signal fpgas revision 4 5-9 advance v1.0 (january 2008) all timing characteristics tables were up dated. for the differential i/o standards, the standard i/o support tables are new. n/a table 2-3 ? array coordinates was updated to change the max x and y values 2-9 table 2-12 ? fusion ccc/pll specification was updated. 2-31 a note was added to table 2-16 rtc acm memory map . 2-37 a reference to the peripheral?s user?s guide was added to the "voltage regulator power supply monitor (vrpsm)" section . 2-42 in table 2-25 ? flash memory block timing , the commercial conditions were updated. 2-55 in table 2-26 ? flashrom access time , the commercial conditions were missing and have been added below the title of the table. 2-58 in table 2-36 ? analog block pin description , the function description was updated for the adcreset. 2-82 in the "voltage monitor" section , the following sentence originally had 10% and it was changed to +10%. the analog quad inputs are tolerant up to 12 v + 10%. in addition, this statement was deleted from the datasheet: each i/o will draw power when connected to power (3 ma at 3 v). 2-86 the "terminology" section is new. 2-88 the "current monitor" section was significantly updated. figure 2-72 ? timing diagram for current monitor strobe to figure 2-74 ? negative current monitor and table 2-37 ? recommended resistor for different current range measurement are new. 2-90 the "adc description" section was updated to add the "terminology" section . 2-93 in the "gate driver" section , 25 ma was changed to 20 ma and 1.5 mhz was changed to 1.3 mhz. in addition, the following sentence was deleted: the maximum ag pad switching frequency is 1.25 mhz. 2-94 the "temperature monitor" section was updated to rewrite most of the text and add figure 2-78 , figure 2-79 , and table 2-38 ? temperature data format . 2-96 in table 2-38 ? temperature data format , the temperature k column was changed for 85c from 538 to 358. 2-98 in table 2-45 ? adc interface timing , "typical-case" was changed to "worst-case." 2-110 the "adc interface timing" section is new. 2-110 table 2-46 ? analog channel specifications was updated. 2-118 the "v cc15a analog power supply (1.5 v)" section was updated. 2-224 the "v ccpla/b pll supply voltage" section is new. 2-225 in "v ccnvm flash memory block power supply (1.5 v)" section , supply was changed to supply input. 2-224 the "v ccpla/b pll supply voltage" pin description was updated to include the following statement: actel recommends tying vccplx to vcc and using proper filtering circuits to decouple v cc noise from pll. 2-225 the "v compla/b ground for west and east pll" section was updated. 2-225 revision changes page
datasheet information 5-10 revision 4 advance 1.0 (continued) in table 2-47 ? adc characteristics in direct input mode , the commercial conditions were updated and note 2 is new. 2-121 the v cc33acap signal name was changed to "xtal1 crystal oscillator circuit input" . 2-228 table 2-48 ? uncalibrated analog channel accuracy* is new. 2-123 table 2-49 ? calibrated analog channel accuracy 1,2,3 is new. 2-124 table 2-50 ? analog channel accuracy: monitoring standard positive voltages is new. 2-125 in table 2-57 ? voltage polarity control truth table?av (x = 0), ac (x = 1), and at (x = 3)* , the following i/o bank names were changed: hot-swap changed to standard lvds changed to advanced 2-131 in table 2-58 ? prescaler op amp power-down truth table?av (x = 0), ac (x = 1), and at (x = 3) , the following i/o bank names were changed: hot-swap changed to standard lvds changed to advanced 2-132 in the title of table 2-64 ? i/o standards supported by bank type , lvds i/o was changed to advanced i/o. 2-134 the title was changed from "fusion standard, lvds, and standard plus hot-swap i/o" to table 2-68 ? fusion standard and advanced i/o features . in addition, the table headings were all updated. the heading used to be standard and lvds i/o and was changed to advanced i/o. standard hot-swap was changed to just standard. 2-136 this sentence was deleted from the "slew rate control and dr ive strength" section : the standard hot-swap i/os do not support slew rate control. in addition, these references were changed: ? from: fusion hot-swap i/o (table 2-69 on page 2-122) to: fusion standard i/o ? from: fusion lvds i/o (table 2-70 on page 2-122) to: fusion advanced i/o 2-152 the "cold-sparing support" section was significantly updated. 2-143 in the title of table 2-75 ? fusion standard i/o standards?out_drive settings , hot-swap was changed to standard. 2-153 in the title of table 2-76 ? fusion advanced i/o standards?slew and out_drive settings , lvds was changed to advanced. 2-153 in the title of table 2-81 ? fusion standard and advanced i/o attributes vs. i/o standard applications , lvds was changed to advanced. 2-157 in figure 2-111 ? naming conventions of fusion devices with three digital i/o banks and figure 2-112 ? naming conventions of fusion devices with four i/o banks the following names were changed: hot-swap changed to standard lvds changed to advanced 2-160 the figure 2-113 ? timing model was updated. 2-161 in the notes for table 2-86 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions , t j was changed to t a . 2-166 revision changes page
fusion family of mixed signal fpgas revision 4 5-11 advance v1.0 (continued) this change table states that in the "208-pin pqfp" table listed under the advance v0.8 changes, the afs090 device had a pin change. that is incorrect. pin 102 was updated for afs250 and afs600. the function name changed from v cc33acap to v cc33a . 3-8 advance v0.9 (october 2007) in the "package i/os: single-/double-ended (analog)" table , the afs1500/m7afs1500 i/o counts were updated for the following devices: fg484: 223/109 fg676: 252/126 ii in the "108-pin qfn" table , the function changed from v cc33acap to v cc33a for the following pin: b25 3-2 in the "180-pin qfn" table , the function changed from v cc33acap to v cc33a for the following pins: afs090: b29 afs250: b29 3-4 in the "208-pin pqfp" table , the function changed from v cc33acap to v cc33a for the following pins: afs090: 102 afs250: 102 3-8 in the "256-pin fbga" table , the function changed from v cc33acap to v cc33a for the following pins: afs090: t14 afs250: t14 afs600: t14 afs1500: t14 3-12 advance v0.9 (continued) in the "484-pin fbga" table , the function changed from v cc33acap to v cc33a for the following pins: afs600: ab18 afs1500: ab18 3-20 in the "676-pin fbga" table , the function changed from v cc33acap to v cc33a for the following pins: afs1500: ad20 3-28 advance v0.8 (june 2007) figure 2-16 ? fusion clocking options and the "rc oscillator" section were updated to change gnd_osc and vcc_os c to gndosc and vccosc. 2-20 , 2-21 figure 2-19 ? fusion ccc options: global buffers with the pll macro was updated to change the positions of oadivrst and oadivhalf, and a note was added. 2-25 the "crystal oscillator" section was updated to include information about controlling and enabling/disabling the crystal oscillator. 2-22 table 2-11 electrical characteristics of the crystal oscillator was updated to change the typical value of i dynxtal for 0.032?0.2 mhz to 0.19. 2-24 the "1.5 v voltage regulator" section was updated to add "or floating" in the paragraph stating that an external pull-down is required on trst to power down the vr. 2-41 the "1.5 v voltage regulator" section was updated to include information on powering down with the vr. 2-41 revision changes page
datasheet information 5-12 revision 4 advance v0.8 (continued) this sentence was updated in the "no-glitch mux (ngmux)" section to delete gla: the glmuxcfg[1:0] configuration bits determ ine the source of the clk inputs (i.e., internal signal or glc). 2-32 in table 2-13 ? ngmux configuration and selection table , 10 and 11 were deleted. 2-32 the method to enable sleep mode was updated for bit 0 in table 2-16 ? rtc control/status register . 2-38 s2 was changed to d2 in figure 2-39 ? read waveform (pipe mode, 32-bit access) for rd[31:0] was updated. 2-51 the definitions for bits 2 and 3 were updated in table 2-24 ? page status bit definition . 2-52 figure 2-46 ? flashrom timing diagram was updated. 2-58 table 2-26 ? flashrom access time is new. 2-58 figure 2-55 ? write access after write onto same address , figure 2-56 ? read access after write onto same address , and figure 2-57 ? write access after read onto same address are new. 2-68 ? 2-70 table 2-31 ? ram4k9 and table 2-32 ? ram512x18 were updated. 2-71 , 2-72 the varef and sample functions were updated in table 2-36 ? analog block pin description . 2-82 the title of figure 2-72 ? timing diagram for current monitor strobe was updated to add the word "positive." 2-91 the "gate driver" section was updated to give information about the switching rate in high current drive mode. 2-94 the "adc description" section was updated to include information about the sample and busy signals and the maximum frequencies for sysclk and adcclk. eq 2 was updated to add parentheses around the entire expression in the denominator. 2-102 table 2-46 analog channel specifications and table 2-47 adc characteristics in direct input mode were updated. 2-118 , 2-121 the note was removed from table 2-55 ? analog multiplexer truth table?av (x = 0), ac (x = 1), and at (x = 3) . 2-131 table 2-63 ? internal temperature monitor control truth table is new. 2-132 the "cold-sparing support" section was updated to add information about cases where current draw can occur. 2-143 figure 2-104 ? solution 4 was updated. 2-147 table 2-75 ? fusion standard i/o standards?out_drive settings was updated. 2-153 the "gnda ground (analog)" section and "gndaq ground (analog quiet)" section were updated to add information about maximum differential voltage. 2-224 the "v aref analog reference voltage" section and "vpump programming supply voltage" section were updated. 2-226 the "v ccpla/b pll supply voltage" section was updated to include information about the east and west plls. 2-225 the v complf pin description was deleted. n/a the "axy analog input/output" section was updated with information about grounding and floating the pin. 2-226 revision changes page
fusion family of mixed signal fpgas revision 4 5-13 advance v0.8 (continued) the voltage range in the "vpump programming supply voltage" section was updated. the parenthetical reference to "pulled up" was removed from the statement, "vpump can be left floating or can be tied (pulled up) to any voltage between 0 v and 3.6 v." 2-225 the "atrtnx temperature monitor return" section was updated with information about grounding and floating the pin. 2-226 the following text was deleted from the "vref i/o voltage reference" section : (all digital i/o). 2-225 the "ncap negative capacitor" section and "pcap positive capacitor" section were updated to include information about the type of capacitor that is required to connect the two. 2-228 1 f was changed to 100 pf in the "xtal1 crystal oscillator circuit input" . 2-228 the "programming" section was updated to include information about v ccosc . 2-229 the vmv pins have now been tied internally with the v cci pins. n/a the afs090 "108-pin qfn" table was updated. 3-2 the afs090 and afs250 devices were updated in the "108-pin qfn" table . 3-2 the afs250 device was updated in the "208-pin pqfp" table . 3-8 the afs600 device was updated in the "208-pin pqfp" table . 3-8 the afs090, afs250, afs600, and afs1500 devices were updated in the "256-pin fbga" table . 3-12 the afs600 and afs1500 devices were updated in the "484-pin fbga" table . 3-20 advance v0.7 (january 2007) the afs600 device was updated in the "676-pin fbga" table . 3-28 the afs1500 digital i/o count was updated in the "fusion family" table . i the afs1500 digital i/o count was updated in the "package i/os: single-/double- ended (analog)" table . ii advance v0.6 (october 2006) the second paragraph of the "pll macro" section was updated to include information about powerdown. 2-30 the description for bit 0 was updated in table 2-17 rtc control/status register . 2-38 3.9 was changed to 7.8 in the "crystal oscillator (xtal osc)" section . 2-40 . all function descriptions in table 2-18 signals for vrpsm macro . 2-42 in table 2-19 ? flash memory block pin names , the rd[31:0] description was updated. 2-43 the "reset" section was updated. 2-61 the "reset" section was updated. 2-64 table 2-35 ? fifo was updated. 2-79 the varef function description was updated in table 2-36 ? analog block pin description . 2-82 the "voltage monitor" section was updated to include information about low power mode and sleep mode. 2-86 the text in the "current monitor" section was changed from 2 mv to 1 mv. 2-90 the "gate driver" section was updated to include information about forcing 1 v on the drain. 2-94 revision changes page
datasheet information 5-14 revision 4 advance v0.6 (continued) the "analog-to-digital converter block" section was updated with the following statement: "all results are msb justified in the adc." 2-99 the information about the adcstart signal was updated in the "adc description" section . 2-102 table 2-46 analog channel specifications was updated. 2-118 table 2-47 adc characteristics in direct input mode was updated. 2-121 table 2-51 ? acm address decode table for analog quad was updated. 2-127 in table 2-53 ? analog quad acm byte assignment , the function and default setting for bit 6 in byte 3 was updated. 2-130 the "introduction" section was updated to include information about digital inputs, outputs, and bibufs. 2-133 in table 2-69 ? fusion pro i/o features , the programmable delay descriptions were updated for the following features: single-ended receiver voltage-referenced differential receiver lvds/lvpecl differential receiver features 2-137 the "user i/o naming convention" section was updated to include "v" and "z" descriptions 2-159 the "v cc33pmp analog power supply (3.3 v)" section was updated to include information about avoiding high current draw. 2-224 the " vccnvm flash memory block powe r supply (1.5 v)" section was updated to include information about avoiding high current draw. 2-224 the "vmvx i/o supply voltage (quiet)" section was updated to include this statement: vmv and vcci must be connec ted to the same power supply and v cci pins within a given i/o bank. 2-185 the "pub push button" section was updated to include information about leaving the pin floating if it is not used. 2-228 the "ptbase pass transistor base" section was updated to include information about leaving the pin floating if it is not used. 2-228 the "ptem pass transistor emitter" section was updated to include information about leaving the pin floating if it is not used. 2-228 the heading was incorrect in the "208-pin pqfp" table . it should be afs250 and not afs090. 3-8 revision changes page
fusion family of mixed signal fpgas revision 4 5-15 advance v0.5 (june 2006) the low power modes of operation were updated and clarified. n/a the afs1500 digital i/o count was updated in table 1 ? fusion family . i the afs1500 digital i/o count was updated in the "package i/os: single-/double- ended (analog)" table . ii the "voltage regulator power supply monitor (vrpsm)" was updated. 2-36 figure 2-45 ? flashrom timing diagram was updated. 2-53 the "256-pin fbga" table for the afs1500 is new. 3-12 advance v0.4 (april 2006) the g was moved in the "product ordering codes" section . iii advance v0.3 (april 2006) the "features and benefits" section was updated. i the "fusion family" table was updated. i the "package i/os: single-/double-ended (analog)" table was updated. ii the "product ordering codes" table was updated. iii the "temperature grade offerings" table was updated. iv the "general description" section was updated to include arm information. 1-1 figure 2-46 ? flashrom timing diagram was updated. 2-58 the "flashrom" section was updated. 2-57 the "reset" section was updated. 2-61 the "reset" section was updated. 2-64 figure 2-27 real-time counter system was updated. 2-35 table 2-19 ? flash memory block pin names was updated. 2-43 figure 2-33 ? flash memory block diagram was updated to include aux block information. 2-45 figure 2-34 ? flash memory block organization was updated to include aux block information. 2-46 the note in the "program operation" section was updated. 2-48 figure 2-76 ? gate driver example was updated. 2-95 the "analog quad acm description" section was updated. 2-130 information about the maximum pad input frequency was added to the "gate driver" section . 2-94 figure 2-65 ? analog block macro was updated. 2-81 figure 2-65 ? analog block macro was updated. 2-81 the "analog quad" section was updated. 2-84 the "voltage monitor" section was updated. 2-86 the "direct digital input" section was updated. 2-89 the "current monitor" section was updated. 2-90 information about the maximum pad input frequency was added to the "gate driver" section . 2-94 revision changes page
datasheet information 5-16 revision 4 advance v0.3 (continued) the "temperature monitor" section was updated. 2-96 eq 2 is new. 2-103 the "adc description" section was updated. 2-102 figure 2-16 ? fusion clocking options was updated. 2-20 table 2-46 analog channel specifications was updated. 2-118 the notes in table 2-72 ? fusion standard and advanced i/o ? hot-swap and 5 v input tolerance capabilities were updated. 2-144 the "simultaneously switching outputs and pcb layout" section is new. 2-149 lvpecl and lvds were updated in table 2-81 ? fusion standard and advanced i/o attributes vs. i/o standard applications . 2-157 lvpecl and lvds were updated in table 2-82 ? fusion pro i/o attributes vs. i/o standard applications . 2-158 the "timing model" was updated. 2-161 all voltage-referenced minimum and maximum dc input and output level tables were updated. n/a all timing characteristic tables were updated n/a table 2-83 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions was updated. 2-165 table 2-79 ? summary of i/o timing char acteristics ? softwa re default settings was updated. 2-134 table 2-93 ? i/o output buffer maximum resistances 1 was updated. 2-171 the "blvds/m-lvds" section is new. blvds and m-lvds are two new i/o standards included in the datasheet. 2-211 the "coremp7 and cortex-m1 software tools" section is new. 2-257 table 2-83 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions was updated. 2-165 table 2-79 ? summary of i/o timing char acteristics ? softwa re default settings was updated. 2-134 table 2-93 ? i/o output buffer maximum resistances 1 was updated. 2-171 the "blvds/m-lvds" section is new. blvds and m-lvds are two new i/o standards included in the datasheet. 2-211 the "108-pin qfn" table for the afs090 device is new. 3-2 the "180-pin qfn" table for the afs090 device is new. 3-4 the "208-pin pqfp" table for the afs090 device is new. 3-8 the "256-pin fbga" table for the afs090 device is new. 3-12 the "256-pin fbga" table for the afs250 device is new. 3-12 revision changes page
fusion family of mixed signal fpgas revision 4 5-17 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "fusion device status" table , is designated as either "product brief," "advance," "preliminary," or "production." the definiti ons of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the products described in this advance status document may not have completed the microsemi qualification process. products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult the microsemi soc products group terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available at http://www.microsemi.com/s oc/documents/ort_report.pdf . microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local sales office for additional reliability information.
51700092-4/01.13 ? 2013 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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